View GL843_4114346.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ru.4 Xu062 f
Genesys Logic, Inc.
GL843
High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
For 3x Series
Datasheet Revision 1.02 Mar. 13, 2006
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Copyright:
Copyright (c) 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc..
Disclaimer:
ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registrated trademark of Genesys Logic Inc.. All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 2
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Revision History
Revision 1.00 1.01 1.02 Date 04/14/2005 11/10/2005 03/13/2006 First formal release Add 208 QFP PinOut, Pin List, Package Dimension Delete"VESD", Table 7.1, P.81 Description
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 3
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
TABLE OF CONTENTS CHAPTER 1 CHAPTER 2 CHAPTER 3 GERERAL DESCRIPTION................................................. 6 FEATURES ........................................................................... 7 PIN ASSIGNMENT .............................................................. 9
3.1 PINOUTS .................................................................................................. 9 3.2 PIN LIST ................................................................................................ 11 3.3 PIN DESCRIPTIONS ................................................................................ 14 CHAPTER 4 REGISTERS........................................................................ 17 4.1 REGISTERS BASE ADDRESS ................................................................... 17 4.2 REGISTER DESCRIPTIONS...................................................................... 21 4.3 REGISTER MAPPING.............................................................................. 64 4.3.1 Shading Mapping (Chunky for Single Bank).............................. 64 4.3.2 Shading Mapping (Chunky for Double Bank)............................ 64 4.3.3 Image Buffer Mapping ................................................................. 65 CHAPTER 5 BLOCK DIAGRAM............................................................ 68 5.1 USB2.0 SYSTEM BLOCK DIAGRAM ....................................................... 68 5.2 FUNCTION BLOCK DIAGRAM ................................................................ 68 CHAPTER 6 CHAPTER 7 FUNCTIONAL DESCRIPTION ........................................ 69 ELECTRICAL CHARACTERISTICS.............................. 81
7.1 ABSOLUTE MAXIMUM RATINGS (VOLTAGE REFERENCED TO GND) ... 81 7.2 DC CHARACTERISTICS (DIGITAL PINS): 3.3 V LOGIC CORE OR PADS . 81 7.3 DC CHARACTERISTICS (DIGITAL PINS): 5.0 V PADS ............................ 82 7.4 DC CHARACTERISTICS (D+/D-) ............................................................ 82 CHAPTER 8 PACKAGE DIMENSION................................................... 83
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 4
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
LIST OF FIGURES
FIGURE 3.1 - 128 PIN QFP PINOUT DIAGRAM .................................................................9 FIGURE 3.1 - 208 PIN QFP PINOUT DIAGRAM ...............................................................10 FIGURE 5.1 - USB2.0 SYSTEM BLOCK DIAGRAM ...........................................................68 FIGURE 5.2 - FUNCTION BLOCK DIAGRAM.....................................................................68 FIGURE 8.1 - GL843 128 PIN QFP PACKAGE .................................................................83 FIGURE 8.2- GL843 208 PIN QFP PACKAGE..................................................................84
LIST OF TABLES
TABLE 3.1 - 128 PIN LIST...............................................................................................11 TABLE 3.2 - 208 PIN LIST...............................................................................................12 TABLE 3.3 - PIN DESCRIPTIONS......................................................................................14 TABLE 4.1 - BASE ADDRESS FOR REGISTERS..................................................................17 TABLE 4.2 - SHADING MAPPING (CHUNKY FOR SINGLE BANK)......................................64 TABLE 4.3 - SHADING MAPPING (CHUNKY FOR DOUBLE BANK) ....................................64 TABLE 4.4 - IMAGE BUFFER MAPPING ...........................................................................65 TABLE 7.1 - ABSOLUTE MAXIMUM RATINGS (VOLTAGE REFERENCED TO GND)..........81 TABLE 7.2 - DC CHARACTERISTICS (DIGITAL PINS): 3.3 V LOGIC CORE OR PADS........81 TABLE 7.3 - DC CHARACTERISTICS (DIGITAL PINS): 5.0 V PADS ..................................82 TABLE 7.4 - DC CHARACTERISTICS (D+/D-)..................................................................82
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 5
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 1
GERERAL DESCRIPTION
Genesys Logic's single-chip GL843 (GeneScanTM series) is a high speed, high performance, low cost and rich scalability controller for scanner. It successfully integrates scanner function ASIC and USB 2.0 interface controller into one single-chip. With its high performance design architecture, GL843 is not only ready for supporting CIS or CCD image sensors (600, 1200, 2400, 3200, 3600, 4800dpi resolution) that are used in sheetfed, flatbed or transparency scanners, but is able to co-work with unipolar or bipolar stepping motors. Advanced features of GL843 include five motor acceleration/ deceleration curve tables for high speed motor moving.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 6
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 2
l l l
FEATURES
Highly integrated scanner controller chip (2-in-1; Scanner Controller and USB 2.0 Interface) USB 2.0 High Speed (480Mbit) compliant Designed for sheetfed, flatbed and transparency scanners
l
l l l l l
l
Supports key-matrix with latch function
Embedded RISC CPU for scanning, run-in and diagnostic tests Supports external 24Kbytes flash ROM or internal 24Kbyte mask ROM Firmware download to external flash ROM 12MHz low frequency clock input for better EMI Flexible 3.3V/5V operating voltage for I/O pads
Adjustable working clock of scanner controller for different usage (12M, 24M, 30M, 40M, 48M, 60MHz)
l l l l l l l l l l l l l l l l l l l l
l
Supports linear or stagger CCD, such as NEC, Toshiba or Sony CCD Available sensor types: 600, 1200, 2400, 3200, 3600 and 4800dpi color CIS or CCD Multi-TG control for CCD (separately controls the R/G/B exposure time) Shutter-control for CCD (separately controls the R/G/B exposure time) Supports two scanning types: pixel-by-pixel (pixel rate), line-by-line (line rate) Support 48-bits color, 16-bits gray and 1-bit line-art "True gray" with R, G and B weightings 16 bits white/dark shading and 16-to-8 bits Gamma correction 0.3us per pixel for color scanning under 40MHz working clock 0.2us per pixel for color scanning under 60MHz working clock Supports LCM/LCD interface to display messages Supports RS232 interface for special applications Supports EEPROM (93C46) interface for special applications Supports ADF (Auto-Document-Feeder) function with document, ADF and cover sensors Lossless data compression Lines packing for stagger CCD or R/G/B line differences Fine CDS sampling adjustment to avoid the digital noise influence (8.33ns adjustment) Digital average and hardware deletion for various resolutions Hardware deletion for various resolutions (from 4800~1dpi with 1dpi decrement) Supports 1M*16, 4M*16, 8M*16, 16M*16 and 32M*16 SDRAM
Supports 5 acceleration/deceleration motor tables for high speed motor moving and wall hitting protection
l l l l
Supports controllable bipolar motor in full, half, quarter and eighth steps moving Supports controllable unipolar motor in full and half steps moving Supports V-reference automatic control for motor driver Ics Build-in PWM control phase for unipolar motors Page 7
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
l l l l l
l
Programmable dummy lines to resolve start/stop (discontinuous) problem Watchdog protection for lamp, motor and ASIC Lamp time-out (sleeping) control Supports 21 GPIO pins and 6 GPO pins for 128-pin package Supports 27 GPIO pins and 6 GPO pins for 208-pin package
Supports 2 PWM outputs for flatbed/transparency lamp control with programmable duties and frequencies
l l l
Supports LED blinking Supports back-scanning Supports multi-film scanning
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 8
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 3
3.1 Pinouts
PIN ASSIGNMENT
GPIO8 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 VccCore4 GndCore4 GPIO19 GPIO20 EXTRST_ GND DVCC0 DGND0 RPU AVDD DPF DPH DMF DMH AGND RREF
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
GndIO5 VccIO5 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 MT_PH7 MT_PH6 MT_PH5 MT_PH4 MT_PH3 GndCore3 VccCore3 MT_PH2 MT_PH1 MT_PH0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 GndIO4 VccIO4 SDO SDI SCLK SEN BSMP VSMP MCLK CCD_CK1X CCD_TGX
GL843
QFP - 128
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
CCD_CK3X CCD_CPX CCD_RSX CCD_CK2X CCD_CK4X GndIO3 VccIO3 CCD_TGG CCD_TGB LAMP_SW GndCore2 VccCore2 XPA_SW LED_B HOME ADF_SENR RAMCLK CKE BANK0 BANK1 WEJ CASJ RASJ ABUS0 ABUS1 ABUS2
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
AVCC1 X2 X1 AGND1 DVCC1 DGND1 DBUS15 DBUS14 DBUS13 DBUS12 DBUS11 DBUS10 DBUS9 DBUS8 VccIO1 GndIO1 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 VccCore1 GndCore1 ABUS12 ABUS11 ABUS10 ABUS9 ABUS8 ABUS7 ABUS6 VccIO2 GndIO2 ABUS5 ABUS4 ABUS3
Figure 3.1 - 128 Pin QFP Pinout Diagram
Page 9
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
NC NC NC NC NC FSHD4 GPIO8 GPIO9 FSHD5 GPIO10 GPIO11 GPIO12 FSHD6 GPIO13 GPIO14 GPIO15 FSHD7 GPIO16 GPIO17 GPIO18 GPIO21 VccCore4 GndCore4 GPIO19 GPIO20 GPIO22 EXTRST_ GND DVCC0 DGND0 RPU AVDD DPF DPH DMF DMH AGND RREF NC NC NC NC NC NC NC NC NC NC NC NC NC NC
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
NC NC NC NC NC GndIO5 VccIO5 GPIO7 GPIO6 GPIO5 FSHD3 GPIO4 GPIO3 GPIO2 GPIO1 FSHD2 MT_PH7 MT_PH6 MT_PH5 MT_PH4 FSHD1 MT_PH3 GndCore3 VccCore3 MT_PH2 MT_PH1 MT_PH0 FSHD0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 GndIO4 VccIO4 SDO SDI SCLK SEN BSMP VSMP MCLK CCD_CK1X CCD_TGX NC NC NC NC NC
GL843
QFP - 208
NC NC NC GPIO23 CCD_CK3X GPIO24 CCD_CPX GPIO25 CCD_RSX GPIO26 CCD_CK2X FSH_WEB FSH_OEB CCD_CK4X FSHA14 GndIO3 VccIo3 CCD_TGG FSHA13 FSHA12 CCD_TGB FSHA11 FSHA10 LAMP_SW FSHA9 GndCore2 VccCore2 FSHA8 XPA_SW FSHA7 FSHA6 LED_B FSHA5 FSHA4 HOME FSHA3 FSHA2 ADF_SENR FSHA1 FSHA0 RAMCLK CKE BANK0 BANK1 WEJ CASJ RASJ ABUS0 ABUS1 ABUS2 NC NC
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
NC NC NC NC NC NC NC AVCC1 X2 X1 AGND1 DVCC1 DGND1 DBUS15 DBUS14 DBUS13 DBUS12 DBUS11 DBUS10 DBUS9 DBUS8 VccIO1 GndIO1 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 VccCore1 GndCore1 ABUS12 ABUS11 ABUS10 ABUS9 ABUS8 ABUS7 ABUS6 VccIO2 GndIO2 ABUS5 ABUS4 ABUS3 NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Figure 3.1 - 208 Pin QFP Pinout Diagram
Page 10
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 3.2 Pin List
Table 3.1 - 128 Pin List
Pin# 1 2 3 4 5 6 7 8 9 Pin Name Type Pin# AVCC1 X2 X1 AGND1 DVCC1 DGND1 DBUS15 DBUS14 DBUS13 P O I P P P I/O I/O I/O I/O I/O I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/O P P O O O O O O Pin Name Type Pin# O P P O O O O O O O O O O O O O I/O I O O P P O O O P P O O O O O Pin Name Type Pin# O O O O O O O O I P P I I I I I I I I O O O P P O O O O O Pin Name Type I/O I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P I/O I/O O P P P P I/O I/O I/O I/O P I/O
33 ABUS6 34 VccIO2 35 GndIO2 36 ABUS5 37 ABUS4 38 ABUS3 39 ABUS2 40 ABUS1 41 ABUS0 42 RASJ 43 CASJ 44 WEJ 45 BANK1 46 BANK0 47 CKE 48 RAMCLK 49 ADF_SENR 50 HOME 51 LED_B 52 XPA_SW 53 VccCore2 54 GndCore2 55 LAMP_SW 56 CCD_TGB 57 CCD_TGG 58 VccIO3 59 GndIO3 60 CCD_CK4X 61 CCD_CK2X 62 CCD_RSX 63 CCD_CPX 64 CCD_CK3X
65 CCD_TGX 66 CCD_CK1X 67 MCLK 68 VSMP 69 BSMP 70 SEN 71 SCLK 72 SDI 73 SDO 74 VccIO4 75 GndIO4 76 OP7 77 OP6 78 OP5 79 OP4 80 OP3 81 OP2 82 OP1 83 OP0 84 MT_PH0 85 MT_PH1 86 MT_PH2 87 VccCore3 88 GndCore3 89 MT_PH3 90 MT_PH4 91 MT_PH5 92 MT_PH6 93 MT_PH7 94 GPIO1 95 GPIO2 96 GPIO3
97 GPIO4 98 GPIO5 99 GPIO6 100 GPIO7 101 VccIO5 102 GndIO5 103 GPIO8 104 GPIO10 105 GPIO11 106 GPIO12 107 GPIO13 108 GPIO14 109 GPIO15 110 GPIO16 111 GPIO17 112 GPIO18 113 VccCore4 114 GndCore4 115 GPIO19 116 GPIO20 117 EXTRST_ 118 GND 119 DVCC0 120 DGND0 121 RPU 122 AVDD 123 DPF 124 DPH 125 DMF
10 DBUS12 11 DBUS11 12 DBUS10 13 DBUS9 14 DBUS8 15 VccIO1 16 GndIO1 17 DBUS7 18 DBUS6 19 DBUS5 20 DBUS4 21 DBUS3 22 DBUS2 23 DBUS1 24 DBUS0 25 VccCore1 26 GndCore1 27 ABUS12 28 ABUS11 29 ABUS10 30 ABUS9 31 ABUS8 32 ABUS7
I/O 126 DMH I/O 127 AGND I/O 128 RREF
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 11
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Table 3.2 - 208 Pin List
Pin# 1 2 3 4 5 6 7 8 9
Pin Name Type Pin#
Pin Name Type Pin# P O O O O O O O P P O O O
Pin Name Type Pin# O O I/O O O I O O O O O O O P P O O O O O O O O P P O O O O O O
Pin Name Type
I/O O I/O O I/O
33 GndCore1 34 ABUS12 NC NC NC NC NC AVCC1 X2 P O I P P P I/O I/O I/O I/O I/O I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/O P 35 ABUS11 36 ABUS10 37 ABUS9 38 ABUS8 39 ABUS7 40 ABUS6 41 VccIO2 42 GndIO2 43 ABUS5 44 ABUS4 45 ABUS3 46 NC 47 NC 48 NC 49 NC 50 NC 51 NC 52 NC 53 NC 54 NC 55 ABUS2 56 ABUS1 57 ABUS0 58 RASJ 59 CASJ 60 WEJ 61 BANK1 62 BANK0 63 CKE 64 RAMCLK
65 FSHA0 66 FSHA1 67 ADF_SENR 68 FSHA2 69 FSHA3 70 HOME 71 FSHA4 72 FSHA5 73 LED_B 74 FSHA6 75 FSHA7 76 XPA_SW 77 FSHA8 78 VccCore2 79 GndCore2 80 FSHA9 81 LAMP_SW 82 FSHA10 83 FSHA11 84 CCD_TGB 85 FSHA12 86 FSHA13
97 GPIO25 98 CCD_CPX 99 GPIO24 100 CCD_CK3X 101 GPIO23 102 NC 103 NC 104 NC 105 NC 106 NC 107 NC 108 NC 109 NC 110 CCD_TGX 111 CCD_CK1X 112 MCLK 113 VSMP 114 BSMP 115 SEN 116 SCLK 117 SDI 118 SDO 119 VccIO4 120 GndIO4 121 OP7 122 OP6 123 OP5 124 OP4 125 OP3 126 OP2 128 OP0
10 X1 11 AGND1 12 DVCC1 13 DGND1 14 DBUS15 15 DBUS14 16 DBUS13 17 DBUS12 18 DBUS11 19 DBUS10 20 DBUS9 21 DBUS8 22 VccIO1 23 GndIO1 24 DBUS7 25 DBU6 26 DBUS5 27 DBUS4 28 DBUS3 29 DBUS2 30 DBUS1 31 DBUS0 32 VccCore1
O O O O O O O O I P P I I I I I I I I
O O O O O O O O O O
87 CCD_TGG 88 VccIO3 89 GndIO3 90 FSHA14 91 CCD_CK4X 92 FSH_OEB 93 FSH_WEB 94 CCD_CK2X 95 GPIO26 96 CCD_RSX
I/O 127 OP1
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 12
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
129 FSHD0 130 MT_PH0 131 MT_PH1 132 MT_PH2 133 VccCore3 134 GndCore3 135 MT_PH3 136 FSHD1 137 MT_PH4 138 MT_PH5 139 MT_PH6 140 MT_PH7 141 FSHD2 142 GPIO1 143 GPIO2 144 GPIO3 145 GPIO4 146 FSHD3 147 GPIO5 148 GPIO6 149 GPIO7 150 VccIO5 151 GndIO5 152 NC 153 NC 154 NC 155 NC 156 NC 157 NC 158 NC 159 NC 160 NC I/O 161 NC O O O P P O O O O 162 FSHD4 163 GPIO8 164 GPIO9 165 FSHD5 166 GPIO10 167 GPIO11 169 FSHD6 171 GPIO14 172 GPIO15 193 AGND I/O 194 RREF I/O 195 NC I/O 196 NC I/O 197 NC I/O 198 NC I/O 199 NC I/O 200 NC I/O 201 NC I/O 202 NC I/O 203 NC I/O 204 NC I/O 205 NC I/O 206 NC I/O 207 NC I/O 208 NC I/O P P I/O I/O I/O O P P P ? P I/O I/O I/O I/O P I/O
I/O 168 GPIO12 I/O 170 GPIO13
I/O 173 FSHD7 I/O 174 GPIO16 I/O 175 GPIO17 I/O 176 GPIO18 I/O 177 GPIO21 I/O 178 VccCore4 I/O 179 GndCore4 I/O 180 GPIO19 I/O 181 GPIO20 P P 182 GPIO22 183 EXTRST_ 184 GND 185 DVCC0 186 DGND0 187 RPU 188 AVDD 189 DPF 190 DPH 191 DMF 192 DMH
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 13
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 3.3 Pin Descriptions
Table 3.3 - Pin Descriptions
Pin Name GPIO1~8,10~20 Type I/O Description General Purpose Input/Output, EEPROM serial data clock or LCM data bit0 Bi-polar (3967): MT_PH5=RESETJ MT_PH4=ENABLEJ MT_PH3=DIR MT_PH2=STEP MT_PH1=MS2 MT_PH0=MS1 Bi-polar (3955): MT_PH7=PHASE_A MT_PH6=PHASE_B MT_PH5=D2A MT_PH4=D1A MT_PH3=D0A MT_PH2=D2B MT_PH1=D1B MT_PH0=D0B Bi-polar (1939): MT_PH3=IN1 MT_PH2=IN2 MT_PH1=ENA1 MT_PH0=ENA2 Bi-polar (2916 or 6219): MT_PH5=PHASE1 MT_PH4=PHASE2 MT_PH3=I11 MT_PH2=I01 MT_PH1=I12 MT_PH0=I02 Uni-polar(2003): MT_PH3=PHASE A MT_PH2=PHASE B MT_PH1=PHASE /A MT_PH0=PHASE /B Motor phase 6~7 ADF sensor for ADF Document sensor for ADF
MT_PH0~5
O
MT_PH6~7 ADF_SENR HOME
O I/O I
Pin Name CCD_CK1X CCD_CPX CCD_TGX CCD_CK2X CCD_RSX CCD_CK3X CCD_CK4X
Type O O O O O O O
Description CCD Shift register clock1 or CIS clock output CCD Clamp gate clock or CIS clock output CCD Transfer gate clock for R channel or CIS Line start pulse CCD Shift register clock2 or CIS clock output CCD Reset gate clock or CIS clock output CCD Shift register clock3 CCD Shift register clock4 Page 14
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CCD_TGG CCD_TGB LAMP_SW XPA_SW LED_B O O O O O CCD Transfer gate clock for G channel CCD Transfer gate clock for B channel Flatbed lamp power control or CIS Red LED array control Transparency lamp power control or CIS Green LED array control CIS Blue LED array control
Pin Name OP7~0 SEN SCLK SDI SDO
BSMP VSMP/CDSCLK2
Type I O O O I O O O AFE digital data input Serial interface load pulse
Description
Serial interface clock output Serial data output Serial data input Video sample synchronization pulse Video sample synchronization pulse Master clock.
MCLK/ADCCLK
Pin Name DBUS15~0 ABUS12~0 RASJ CASJ WEJ
BANK0~1 CKE
Type I/O O DRAM data bus DRAM address bus
Description
SDRAM row address strobe O O O O O SDRAM column address strobe SDRAM write enable SDRAM bank select SDRAM clock enable SDRAM clock
RAMCLK
Pin Name X1 X2 EXTRST_
Type I I/O I
Description Clock input for crystal (12MHz) Clock output for crystal Hardware reset input
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 15
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Pin Name RPU
DPF DPH
Type I/O I/O I/O I/O -
Description 3.3V Pull up control for DPF Positive USB differential data (Full Speed) Positive USB differential data (High Speed) Negative USB Differential Data (Full Speed) Negative USB Differential Data (High Speed) 510 reference resistor input
DMF DMH RREF
Pin Name AVDD, AVCC1 AGND, AGND1
DVCC0, DVCC1 DGND0, DGND1
Type P P P P P P P P P P P
Description Analog power input for USB2.0 transceiver 3.3V Analog ground input for USB2.0 transceiver Digital power input for USB2.0 controller 3.3V Digital ground input for USB2.0 controller.
Digital power input for scanner controller logic core 3.3V
VccCore1~4 GndCore1~4, GndIO1~5 VccIO1~2 VccIO3 VccIO4 VccIO5 GND Notation: Type O I B B/I B/O P A SO pu pd odpu odpu
Digital ground input for scanner controller. For Pin7~Pin48 3.3V For Pin49~Pin66 3.3V For Pin67~Pin83 3.3V For Pin84~Pin117 3.3V Ground
Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up Open drain with internal pull up
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 16
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 4
REGISTERS
Table 4.1 - Base Address for Registers
4.1 Registers Base Address
Offset (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
01h CISSET DOGENB DVDSET STAGGER COMPENB TRUEGRAY SHDAREA SCAN 02h NOTHOME ACDCDIS AGOHOME MTRPWR FASTFED MTRREV HOMENEG LONGCURV 03h LAMPDOG AVEENB XPASEL LAMPPWR LAMPTIM[3:0] 04h LINEART BITSET AFEMOD[1:0] FILTER[1:0] FESET[1:0] GMMENB ENB20M 05h DPIHW[1:0] MTLLAMP[1:0] MTLBASE[1:0] 06h SCANMOD[2:0] PWRBIT GAIN4 OPTEST[2:0] 07h
LAMPSIM CCDCTL DRAMCTL MOVCTL RAMSEL FASTDMA DMASEL DMARDWR
8'h94 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h32 8'h14 8'h00 8'h00 8'h00 8'h00 8'h00 8'h04 8'h20 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00
08h X DECFLAG GMMFFR EVEN1ST 09h MCNTSET[1:0] 0Ah LCDSEL LCMSEL ADFSEL 0Bh CLKSET[2:0] 0Ch SWSH[4:0] 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h
JAMPCMD DOCCMD CCDCMD
GMMFFG GMMFFB GMMZR GMMZG GMMZB BLINE1ST BACKSCAN ENHANCE SHORTTG NWAIT LPWMEN EPROMSEL RS232SEL BAUDRAT[1:0] RFHDIS ENBDRAM DRAMSEL[2:0] CCDLMT[2:0 ]
FULLSTP SEND CLRMCNT CLRDOCJM CLRLNCNT
CTRLHI TOSHIBA TGINV TGMODE[1:0] CNSET DCKSEL[1:0]
SCANRESET MOVE EXPR[15:8] EXPR[7:0] EXPG[15:0] EXPG[7:0] EXPB[15:8] EXPB[7:0] CK1INV CK2INV CTRLINV CKDIS CTRLDIS TGW[5:0] CKTOGGLE CKDELAY[1:0] CKSEL[1:0] EXPDMY[7:0] X
1Ah TGLSW2 TGLSW1 MANUAL3 MANUAL1 CK4INV CK3INV LINECLP 1Bh GRAYSET CHANSEL BGRENB ICGENB ICGDLY[3:0]
1Ch CK4MTGL CK3MTGL CK1MTGL CKAREA MTLWD TGTIME[2:0] 1Dh CK4LOW CK3LOW CK1LOW TGSHLD[4:0] 1Eh WDTIME[3:0] LINESEL[3:0] 1Fh SCANFED[7:0] 20h BUFSEL[7:0] 21h STEPNO[7:0] 22h FWDSTEP[7:0] 23h BWDSTEP[7:0] 24h FASTNO[7:0] 25h X X X X LINCNT[19:16] 26h LINCNT[15:8] (c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 17
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
27h LINCNT[7:0] 8'h00 28h "GMMWRDATA" 29h X X X RAMADDR[20:16] 8'h00 2Ah RAMADDR[15:8] 8'h00 2Bh RAMADDR[7: 0] 8'h00 2Ch X X DPISET[13:8] 8'h00 2Dh DPISET[7:0] 8'h00 2Eh BWHI[7:0] 8'h00 2Fh BWLOW[7:0] 8'h00 30h STRPIXEL[15:8] 8'h00 31h STRPIXEL[7:0] 8'h00 32h ENDPIXEL[15:8] 8'h00 33h ENDPIXEL[7:0] 8'h00 34h DUMMY[7:0] 8'h00 35h MAXWD[24:17] 8'h00 36h MAXWD[16:9] 8'h00 37h MAXWD[8:1] 8'h00 38h LPERIOD[15:8] 8'h2A 39h LPERIOD[7:0] 8'h30 FEWRDATA[8] 3Ah X X X X X X X 3Bh FEWRDATA[7:0] 3Ch "RAMWRDATA" 3Dh X X X X FEEDL[19:16] 8'h00 3Eh FEEDL[15:8] 8'h00 3Fh FEEDL[7:0] 8'h00 COVERSNR CHKVER DOCJAM HISPDFLG MOTMFLG DATAENB 40h DOCSNR ADFSNR 41h PWRBIT BUFEMPTY FEEDFSH SCANFSH HOMESNR LAMPSTS FEBUSY MOTORENB 42h VALIDWORD[24:17] 8'h00 43h VALIDWORD[16:9] 8'h00 44h VALIDWORD[8:1] 8'h00 45h "RAMRDDATA" FERDDATA[8] 46h X X X X X X X 47h FERDDATA[7:0] 48h X X X X FEDCNT[19:16] 8'h00 49h FEDCNT[15:8] 8'h00 4Ah FEDCNT[7:0] 8'h00 4Bh X X X X SCANCNT[19:16] 8'h00 4Ch SCANCNT[15:8] 8'h00 4Dh SCANCNT[7:0] 8'h00 4Eh "GMMRDDATA" 4Fh X X DOGON ROMBSY LCMBSY TX232BSY RX232BSY RXREADY 50h X X FERDA[5:0] 8'h00 51h X X FEWRA[5:0] 8'h00 52h X X X RHI[4:0] 8'h00 53h X X X RLOW[4:0] 8'h00 54h X X X GHI[4:0] 8'h00 55h X X X GLOW[4:0] 8'h00 (c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 18
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
56h X X X BHI[4:0] 57h X X X BLOW[4:0] 58h VSMP[4:0] VSMPW[2:0] 59h BSMP[4:0] BSMPW[2:0] 5Ah ADCLKINV RLCSEL CDSREF[1:0] RLC[3:0] 5Bh X MTRTBL GMMADDR[13:8] 5Ch GMMADDR[7:0] 5Dh HISPD[7:0] 5Eh DECSEL[2:0] STOPTIM[4:0] 5Fh FMOVDEC[7:0] 60h X X X Z1MOD[20:16] 61h Z1MOD[15:8] 62h Z1MOD[7:0] 63h X X X Z2MOD[20:16] 64h Z2MOD[15:8] 65h Z2MOD[7:0] 66h PHFREQ[7:0] 67h STEPSEL[1:0] MTRPWM[5:0] 68h FSTPSEL[1:0] FASTPWM[5:0] 69h FSHDEC[7:0] 6Ah FMOVNO[7:0] 6Bh MULTFILM GPOM13 GPOM12 GPOM11 GPOCK4 GOPCP GPOLEDB GPOADF 6Ch GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 6Dh GPIO8 GPIO7 GPOI6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 6Eh GPOE16 GPOE15 GPOE14 GPOE13 GPOE12 GPOE11 GPOE10 GPOE9 6Fh GPOE8 GPOE7 GPOE6 GPOE5 GPOE4 GPOE3 GPOE2 GPOE1 70h X X X RSH[4:0] 71h X X X RSL[4:0] 72h X X X CPH[4:0] 73h X X X CPL[4:0] 74h X X X X X X CK1MAP[17:16] 75h CK1MAP[15:8] 76h CK1MAP[7:0] 77h X X X X X X CK3MAP[17:16] 78h CK3MAP[15:8] 79h CK3MAP[7:0] 7Ah X X X X X X CK4MAP[17:16] 7Bh CK4MAP[15:8] 7Ch CK4MAP[7:0] 7Dh CK1NEG CK3NEG CK4NEG RSNEG CPNEG BSMPNEG VSMPNEG DLYSET 7Eh GPOLED25 GPOLED24 GPOLED23 GPOLED22 GPOLED21 GPOLED10 GPOLED9 GPOLED8 7Fh BSMPDLY[1:0] VSMPDLY[1:0] LEDCNT[3:0] 80h VRHOME[1:0] VRMOVE[1:0] VRBACK[1:0] VRSCAN[1:0] 81h 82h 83h
X X CONTB[3:0] IMGSET[7:0] X LOADSET[4:0] CONTA[3:0]
8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h7F 8'h7F 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h06 8'h08 8'h08 8'h0A 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 19
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
84h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh X X X PACK[1:0] X YENB X X PACKCNT[5:0] ACYCNRLC ENOFFSET LEDADD CK4ADC RDNUM[4:0] RS232WD[7:0] RS232RD[7:0] ROMADDR[7:0] ROMWD[15:8] ROMWD[7:0] ROMRD[15:8] ROMRD[7:0] PREFED[15:8] PREFED[7:0] PSTFED[15:8] PSTFED[7:0] MTRPLS[7:0] X SCANLEN[19:16] SCANLEN[15:8] SCANLEN[7:0] ONDUR[15:8] ONDUR[7:0] OFFDUR[15:8] OFFDUR[7:0] LCMWD[7:0] MULDMYLN RAMDLY[1:0] MOTLAG CMODE STEPTIM[1:0] IFRS X SEL3INV TGSTIME[2:0] TGWTIME[2:0]
LCDCTL LCMCTL EPROMCTL TGCTL MPUCTL
YBIT X
AUTOCONF
8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00
8'h00 8'h00 X
MOTMPU NEC8884 DPI9600
A0h X X LNOFSET[5:0] X A1h X X X STGSET[4:0] X A2h X X X RFHSET[4:0] 8'h00 A3h TRUER[7:0] A4h TRUEG[7:0] A5h TRUEB[7:0] 8'h00 A6h GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 8'h00 A7h GPOE24 GPOE23 GPOE22 GPOE21 GPOE20 GPOE19 GPOE18 GPOE17 8'h00 A8h X X GPOE27 GPOE26 GPOE25 GPO27 GPO26 GPO25 8'h00 A9h X X GPO33 GPO32 GPO31 GPO30 GPO29 GPO28 8'h00 NODECEL TB3TB1 TB5TB2 FIX16CLK 8'h00 ABh GPOM9 MULSTOP[2:0] ACh VRHOME3 VRHOME2 VRMOME3 VRMOME2 VRBACK3 VRBACK2 VRSCAN3 VRSCAN2 8'h00 ADh AEh AFh Notation: R/W R/O X X X X SCANTYP[2:0] ADFTYP[1:0] MOTSET[2:0] FEDTYP[1:0] CCDTYP[3:0] PROCESS[2:0] ADFMOVE[2:0]
Read / Write Read Only Page 20
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
W/O R/W1C R/W/C Write Only Readable and Write-1-Clear Read / Write and hardware automatic Clear
4.2 Register Descriptions
Offset 01h CISSET R/W 7 CISSET 6 DOGENB 5 DVDSET 4 STAGGER DOGENB R/W 0 1 0 1 0 1 DVDSET R/W
STAGGER
R/W
COMPENB TRUEGRAY SHDAREA R/W R/W R/W
SCAN R/W
CCD scan type. CIS scan type. Disable watchdog function. Enable watchdog function (set time out duration in Reg1E[7:4]). Disable shading function. Enable shading function (include whole line shading and area shading).
1 Enable double shading. 0 Disable double shading.
3 COMPENB 2 TRUEGRAY 1 SHDAREA 0 SCAN
0 1 0 1 0 1 0 1
Disable data compression. Enable lossless data compression. Disable true gray function. Enable true gray function. The weightings are stored in Reg A3,A4 and A5. Select whole-line shading. Select area-shading (depend on scan area and scan dpi). Disable scanning process. Enable scanning process.
Offset 02h NOTHOME ACDCDIS AGOHOME MTRPWR R/W R/W R/W R/W 7 NOTHOME FASTFED R/W MTRREV HOMENEG LONGCURV R/W R/W R/W
6 ACDCDIS 5 AGOHOME
4 MTRPWR 3 FASTFED 2 MTRREV 1 HOMENEG
0 LONGCURV
0 In auto-go-home function, carriage will not stop until touching the home sensor. 1 In auto-go-home function, moving steps of carriage depends on steps setting from software (Reg 3D, 3E and 3F). 0 Enable carriage backtracking when image buffer is full. 1 Disable carriage backtracking when image buffer is full. 0 Disable auto-go-home function. 1 Enable auto-go-home function. It's for carriage to go home automatically after scanning finished. 0 Turn off MOTOR power and phase to idle state. 1 Turn on MOTOR power and phase. 0 Move to scanning window by only one acceleration/deceleration tables. 1 Move to scanning window by two acceleration/deceleration tables. 0 Set motor to move in forward direction. 1 Set motor to move in reverse direction. 0 Motor will be decelerated when home sensor input (HOME) changes from low to high (rising edge). 1 Motor will be decelerated when home sensor input (HOME) changes from high to low (falling edge). 0 The deceleration curve of the fast moving is defined in table 4 or use default Page 21
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
curve. 1 The deceleration curve of the fast moving is defined in table 5 to protect wall-hitting. Offset 03h ................................................................................... Default value = 8'h94 LAMPDOG AVEENB R/W R/W 7 LAMPDOG 6 5 4 3-0 XPASEL R/W LAMPPWR LAMPTIM3 LAMPTIM2 LAMPTIM1 LAMPTIM0 R/W R/W R/W R/W R/W
0 To disable sleep mode of lamp. 1 To start sleep mode of lamp (default on). AVEENB 0 Select dpi deletion function 1 Select dpi average function. XPASEL 0 Select flatbed lamp on. 1 Select transparency lamp on. LAMPPWR 0 Turn off LAMP power. 1 Turn on LAMP power. LAMPTIM[3:0] Counter of the sleep mode of lamp (default: 4). The unit is minute.
Offset 04h .................................................................................... Default value = 8'h00 LINEART R/W BITSET R/W AFEMOD1 AFEMOD0 R/W R/W FILTER1 R/W FILTER0 R/W FESET1 R/W FESET0 R/W
0 Color/Gray scanning. 1 Black/White scanning. 6 BITSET 0 8 bits image data type (= byte). 1 16 bits image data type (= word). 5-4 AFEMOD[1:0] AFE operation mode. Wolfson Type CDS AFEMOD SCANMOD Description Max Sample Rate Available Slow color 2 0,1,7 Yes 5MSPS *3 channel Pixel-by-pixel 1 0 0,1,6,7 0,1,4,5,6 Color pixel-by-pixel Fast Mono Yes Yes 6.67MSPS *3 channel 13.3MSPS *1 channel Timing Requirements MCLK:VSMP Rate is 8:1 MCLK:VSMP Rate is 6:1 MCLK:VSMP Rate is 3:1 Timing Requirements MCLK:VSMP Rate is 3:1 MCLK:VSMP Rate is 2:1 MCLK:VSMP Rate is 1:1
7 LINEART
Analog Device Type CDS AFEMOD SCANMOD Description Max Sample Rate Available Slow color 2 0,1,6,7 Yes Pixel-by-pixel 1 0 0,1,6,7 0,1,6,7 Mono Fast Mono Yes Yes
3-2 FILTER[1:0]
Scan color type: 00 Color Page 22
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
01 R 10 G 11 B Front end operation type: 00 ESIC type 1 01 ESIC type2 10 ADI type 11 Reserved
1-0 FESET[1:0]
Offset 05h ..................................................................................... Default value = 8'h00 DPIHW1 R/W DPIHW0 R/W
MTLLAMP1 MTLLAMP0 GMMENB
R/W
R/W
R/W
ENB20M R/W
MTLBASE1 MTLBASE0
R/W
R/W
7-6 DPIHW[1:0]
To set CCD/CIS resolution. 00 600 dpi 01 1200 dpi 10 2400 dpi 11 4800 dpi 5-4 MTLLAMP[1:0] Multiply coefficient for time-out counter of lamp. 00 1* LAMPTIM 01 2* LAMPTIM 10 4* LAMPTIM 11 Reserved 3 GMMENB 0 Disable gamma correction. 1 Enable gamma correction. 2 ENB20M 0 CCD_CK1X output clocks according to designer's settings . 1 CCD_CK1X generate 20MHz clock to CCD or CIS sensors. 1-0 MTLBASE[1:0] To set output CCD pixel number under each system pixel time. 00 1 CCD pixel/sstem pixel time. 01 2 CCD pixel/sstem pixel time. 10 3 CCD pixel/sstem pixel time. 11 4 CCD pixel/sstem pixel time. Offset 06h ..................................................................................... Default value = 8'h00
SCANMOD2 SCANMOD1 SCANMOD0
R/W
R/W
R/W
PWRBIT R/W
GAIN4 R/W
OPTEST2 R/W
OPTEST1 R/W
OPTEST0 R/W
7-5 SCANMOD[2:0] To set operation mode. 000 12 clocks/pixel ; normal mode operation for scanning. Color scanning : 24 bits image with gamma correction Gray scanning : 8 bits image with gamma correction 16 bits image without gamma correction Line art scanning : 1 bit image with gamma correction 001 12 clocks/pixel ; bypass mode operation for calibration. Include color(pixel rate) , gray line-art. 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 18 clocks/pixel. Color scanning : 24 bits image with gamma correction 48 bits image without gamma correction Gray scanning : 8 bits image with gamma correction 16 bits image without gamma correction (c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 23
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Line art scanning : 1 bit image with gamma correction 111 16 clocks/pixel. Color scanning : 24 bits image with gamma correction 48 bits image without gamma correction Gray scanning : 8 bits image with gamma correction 16 bits image without gamma correction Line art scanning : 1 bit image with gamma correction The hardware will reset this bit during power-on initial process. It can be set and checked by S/W to know if the power had been turned off or not. Default is reset. 0 Digital shading gain=8 times system. 1 Digital shading gain=4 times system. Note: If you want to get more precise image quality,you can set GAIN4 bit. Select ASIC operation type. 000 Set normal mode to capture AFE image. 001 Set SDRAM bank testing and power-on moving testing for ASIC simulation 010 Pixel count pattern for ASIC image test. 011 Line count pattern for ASIC image test. 100 Counter and adder test for ASIC simulation test. 101 Reserved. 110 Reserved. 111 Reserved.
4 PWRBIT
3 GAIN4
2-0 OPTEST[2:0]
Offset 07h ..................................................................................... Default value = 8'h00
LAMPSIM CCDCTL DRAMCTL MOVCTL RAMSEL FASTDMA DMASEL DMARDWR
R/W 7 6 5 4 3 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LAMPSIM CCDCTL DRAMCTL MOVCTL SRAMSEL FASTDMA
1 0
DMASEL DMARDWR
for timer simulation for CCD timing control for SRAM & DRAM access control for motor driver IC style control 0 DMA access for DRAM. 1 DMA access for SRA 0 4clocks/access,that is to say 4clocks/16bits or 4clocks/8bits for DMA access. 1 2clocks/access,that is to say 2clocks/16bits or 2clocks/8bits for DMA access. 0 MPU access DRAM under command mode. 1 DMA access DRAM under command mode. 0 DMA read DRAM under command mode.
Note: Please do not write other values than 00H into this register under normal condition. Offset 08h ..................................................................................... Default value = 8'h00 X X DECFLAG GMMFFR R/W R/W 0 1 0 1 GMMFFG R/W GMMFFB R/W GMMZR R/W GMMZG R/W GMMZB R/W
7 RESERVED 6 DECFLAG 5 GMMFFR
Select gamma table in increment type Select gamma table in decrement type. This function is not enabled Gamma table address FFH of red channel is a special value. Page 24
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
4 GMMFFG 3 GMMFFB 2 GMMZR 0 1 0 1 0 1 0 1 0 1 This function is not enabled. Gamma table address FFH of green channel is a special value. This function is not enabled. Gamma table address FFH of blue channel is a special value. This function is not enabled. Gamma table address 00H of red channel is a special value. This function is not enabled. Gamma table address 00H of green channel is a special value. This function is not enabled. Gamma table address 00H of blue channel is a special value.
1 GMMZG 0 GMMZB
Offset 09h ..................................................................................... Default value = 8'h00
MCNTSET1 MCNTSET0 EVEN1ST BLINE1ST BACKSCAN ENHANCE SHORTTG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NWAIT R/W
7-6 MCNTSET[1:0] To select the unit of motor table counter. 00 Pixel count. 01 System clock*2. 10 System clock*3. 11 System clock*4. 5 EVEN1ST 0 The first pixel of stagger CCD is located at odd sensor line. 1 The first pixel of stagger CCD is located at even sensor line. 4 BLINE1ST 0 The first sensor of CCD is red line. 1 The first sensor of CCD is blue line. 3 BACKSCAN 0 Select forward scanning function. 1 Select backward scanning function. 2 ENHANCE 0 Select normal mode for embedded EPP interface. 1 Select enhance mode for embedded EPP interface. 1 SHORTTG 0 Disable this function. 1 Enable short CCD SH(TG) period for film scanning. 0 NWAIT 0 No delay for nWait. 1 To delay nWait (H_BUSY) for one clock. Offset 0Ah .................................................................................. Default value = 8'h00 LCDSEL R/W LCMSEL R/W 0 1 0 1 0 1 0 1 0 1 ADFSEL R/W LPWMEN EPROMSEL RS232SEL BAUDRAT1 BAUDRAT0 R/W R/W R/W R/W R/W
7 LCDSEL 6 LCMSEL 5 ADFSEL 4 LPWMEN 3 EPROMSEL
2 RS232SEL
Disable LCD display function. Enable LCD display function and the specific GPIOs are defined to drive LCD. Disable LCM display function. Enable LCM display function and the specific GPIOs are defined to drive LCM. Disable ADF function. Enable ADF function and the specific GPIOs are defined to drive ADF module. Disable ADF function. Enable PWM function of lamp. Disable external EEPROM (93C46) interface. Enable external EEPROM (93C46) interface and the specific GPIOs are defined to connect EEPROM. 0 Disable RS232 interface. Page 25
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
1 Enable RS232 interface for special application and the specific GPIOs are defined to implement RS232 protocol. 1-0 BAUDRAT[1:0] Set boud rate of RS232. 00 2400bps. 01 4800bps. 10 9600bps. 11 19200bps. Offset 0Bh .................................................................................. Default value = 8'h00 CLKSET2 R/W CLKSET1 R/W CLKSET0 R/W RFHDIS R/W
ENBDRAM DRAMSEL2 DRAMSEL1 DRAMSEL0
R/W
R/W
R/W
R/W
7-5 CLKSET[2:0]
To select the system clock frequency. 000 24MHz. 001 30MHz. 010 40MHz. 011 48MHz. 100 60MHz. 101 Reserved. 110 Reserved. 111 Reserved. 4 RFHDIS 0 Enable auto-refresh mode for SDRAM. 1 Enable self-refresh mode for SDRAM. 3 ENBDRAM A rising edge from low to high: to start power on sequence of SDRAM. 2-0 DRAMSEL[2:0] Select the SDRAM size. 000 Reserved. 001 16M bit. 010 64M bit. 011 128M bit. 100 256M bit. 101 512M bit. 110 Reserved. 111 Reserved.
Offset 0Ch .................................................................................. Default value = 8'h00
SWSH4 SWSH3 SWSH2 SWSH1 SWSH0 CCDLMT2 CCDLMT1 CCDLMT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W the width s
R/W
7-3 SWSH [4:0]
To set the distance from SEL3 to TG for NEC8884. SWSH[4:2]*2 TGSTIME
2-0 CCDLMT[2:0] Offset 0Dh
To set the lines count which is synchronized for CCD timing(like NEC8884).
JAMPCMD DOCCMD CCDCMD W W W
FULLSTP W
SEND W
CLRMCNT
CLRDOCJM
CLRLNCNT
W
W
W
Command: Scanner command. 7 JAMPCMD To control jamp when scanner is working on ADF.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 26
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
6 DOCCMD 5 CCDCMD 4 3 2 1 FULLSTP SEND CLRMCNT CLRDOCJM To control document when scanner is working on ADF. To control CCD when abnormal status happens.
To reset steps type to full step. To send the RS232 data. To clear FEDCNT(Reg48,Reg49,Reg4A) counter information. 0 Don't clear document jam message for ADF module. 1 To clear document jam message for ADF module. 0 CLRLNCNT 0 Don't clear SCANCNT. 1 To clear SCANCNT (Reg4B,Reg4C,Reg4D). Note: 1.For each scanning, designers must clear SCANCNT before starting process. 2.Other bits in this register are not defined.
Offset 0Eh
SCANRESET
W Command: Scanner software reset. It can initiate AISC system including lamp and motor, control registers, internal circuit; but not including tables in DRAM, like gamma table, shading table and acceleration/deceleration table. Note: In normal condition, it is unnecessary to reset scanner unless the scanner is out of control. Offset 0Fh
MOVE
W Command: Motor moving. Start motor forward/backward moving. Offset 10h ..................................................................................... Default value = 8'h00 EXPR15 R/W EXPR14 R/W EXPR13 R/W EXPR12 R/W EXPR11 R/W EXPR10 R/W EXPR9 R/W EXPR8 R/W
7-0 EXPR[15:8] Exposure time setting (in pixel time) for Red-LED of CIS or Red channel of CCD. Note: It cannot be programmed to logic zero. Offset 11h ..................................................................................... Default value = 8'h00 EXPR7 R/W EXPR6 R/W EXPR5 R/W EXPR4 R/W EXPR3 R/W EXPR2 R/W EXPR1 R/W EXPR0 R/W
7-0 EXPR[7:0] Exposure time setting (in pixel time) for Red-LED of CIS or Red channel of CCD. Note: It cannot be programmed to logic zero. Offset 12h ..................................................................................... Default value = 8'h00 EXPG15 R/W EXPG14 R/W EXPG13 R/W EXPG12 R/W EXPG11 R/W EXPG10 R/W EXPG9 R/W EXPG8 R/W Page 27
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
7-0 EXPG[15:8] Exposure time setting (in pixel time) for Green-LED of CIS or Red channel of CCD. Note: It cannot be programmed to logic zero. Offset 13h ..................................................................................... Default value = 8'h00 EXPG7 R/W EXPG6 R/W EXPG5 R/W EXPG4 R/W EXPG3 R/W EXPG2 R/W EXPG1 R/W EXPG0 R/W
7-0 EXPG[7:0] Exposure time setting (in pixel time) for Green-LED of CIS or Red channel of CCD. Note: It cannot be programmed to logic zero. Offset 14h ..................................................................................... Default value = 8'h00 EXPB15 R/W EXPB14 R/W EXPB13 R/W EXPB12 R/W EXPB11 R/W EXPB10 R/W EXPB9 R/W EXPB8 R/W
7-0 EXPB[15:8] Exposure time setting (in pixel time) for Blue-LED of CIS or Red channel of CCD. Note: It cannot be programmed to logic zero. Offset 15h ..................................................................................... Default value = 8'h00 EXPB7 R/W EXPB6 R/W EXPB5 R/W EXPB4 R/W EXPB3 R/W EXPB2 R/W EXPB1 R/W EXPB0 R/W
7-0 EXPB[7:0] Exposure time setting (in pixel time) for Blue-LED of CIS or Red channel of CCD. Note: It cannot be programmed to logic zero. Offset 16h ..................................................................................... Default value = 8'h32 CTRLHI R/W TOSHIBA R/W 0 1 0 1 0 1 0 1 0 1 0 1 0 TGINV R/W CK1INV R/W CK2INV R/W CTRLINV R/W CKDIS R/W CTRLDIS R/W
7 CTRLHI 6 TOSHIBA 5 TGINV 4 CK1INV 3 CK2INV 2 CTRLINV 1 CKDIS
CCD CP & RS will be low when TG goes high. CCD CP & RS will be high when TG goes high. Not TOSHIBA CIS. To indicate the image sensor is TOSHIBA CIS. Don't reverse. To reverse CCD TG. Don't reverse. To reverse CCD Clock 1. Don't reverse. To reverse CCD Clock 2. Don't reverse. To reverse CCD CP & RS. Disable clock1 and 2 under CCD TG position as illustrated.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 28
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
0 Enable clock 1 and 2 under CCD TG position as illustrated.
0 CTRLDIS
1 Disable CCD CP & RS signals under CCD TG position as illustrated.
0
Enable CCD CP & RS signals under CCD TG position as illustrated.
Offset 17h .................................................................................... Default value = 8'h14 TGMODE1 TGMODE0 R/W R/W TGW5 R/W TGW4 R/W TGW3 R/W TGW2 R/W TGW1 R/W TGW0 R/W
7-6 TGMODE[1:0] To set CCD TG mode. 00 normal CCD TG type. 01 CCD TG control with dummy line. 10 CCD TG control with dummy lines for transparency scanning type. 11 reserved for ASIC simulation. 5-0 TGW[5:0] To set CCD TG plus width (in pixel time). Note: It cannot be programmed to logic zero. Offset 18h ..................................................................................... Default value = 8'h00 CNSET R/W 7 CNSET DCKSEL1 DCKSEL0 CKTOGGLE CKDELAY1 CKDELAY0 R/W R/W R/W R/W R/W CKSEL1 R/W CKSEL0 R/W
0 1 6-5 DCKSEL1[1:0] 00 01 10
Select TG and clock to be non-Canon CIS style. Select TG and clock to be Canon CIS style. Speed 1: one CCD clock per system pixel time in shifting dummy lines. Speed 2: two CCD clock per system pixel time in shifting dummy lines. Speed 3: three CCD clock per system pixel time in shifting dummy lines. Page 29
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
11 Speed 4: four CCD clock per system pixel time in shifting dummy lines. 4 CKTOGGLE 0 One cycle per pixel. 1 Half cycle per pixel for CCD clock 1 & 2. 3-2 CKDELAY[1:0] 00 No delay 01 Delay one system clock for CCD Clock 1/2. 10 Delay two systems clock for CCD Clock 1/2. 11 Delay three systems clock for CCD Clock 1/2. 1-0 CKSEL[1:0] 00 Speed 1: one CCD clock per system pixel time in capturing image. 01 Speed 2: two CCD clock per system pixel time in capturing image. 10 Speed 3: three CCD clock per system pixel time in capturing image. 11 Speed 4: four CCD clock per system pixel time in capturing image. Note: Speed limitation of CCD clock in different scanning modes: 1. SCANMOD=0,1 : 12 clocks/pixel a. toggle CCD : supports speed 1,2,3,4. b. non-toggle CCD : supports speed 1,2,3. 2. SCANMOD=2 : Reserved. 3. SCANMOD=3 : Reserved. 4. SCANMOD=4 : Reserved. 5. SCANMOD=5 : Reserved. 6. SCANMOD=6 : 18 clocks/pixel a. toggle CCD : supports speed 1,2,3. b. non-toggle CCD : supports speed 1,2,3,4. 7. SCANMOD=7 : 16 clocks/pixel a. toggle CCD : supports speed up 1,2,4. b. non-toggle CCD : supports speed 1,2,4. Note: Toggle CCD a CCD which can output one pixel in one half cycle of CCD clock. Non-toggle CCD a CCD which always output one pixel in one CCD clock cycle. Offset 19h ................................................................................... Default value = 8'h00 EXPDMY7 EXPDMY6 EXPDMY5 EXPDMY4 EXPDMY3 EXPDMY2 EXPDMY1 EXPDMY0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 EXPDMY[7:0] To set exposure time of dummy lines (unit = 256 pixels time) or CIS LED turn-on tme. CIS SP CIS LED EXPDMY for turn on Note: It cannot be programmed to logic zero. EXPR/EXPG/EXPB for turn off
Offset 1Ah .................................................................................. Default value = 8'h00 TGLSW2 R/W 7 TGLSW2 6 TGLSW1 TGLSW1 R/W MANUAL3 MANUAL1 R/W R/W CK4INV R/W CK3INV R/W LINECLP R/W X X
Set CCD SW2 output. Set CCD SW1 output. 0 1 0 1 CCD Clock 3,Clock4 automatic output. CCD Clock 3,Clock4 manual output. CCD Clock 1,Clock2 automatic output. CCD Clock 1,Clock2 manual output. Page 30
5 MANUAL3 4 MANUAL1
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
3 CK4INV 2 CK3INV 1 LINECLP 0 RESERVED 0 1 0 1 0 1 Don't reverse. To reverse CCD Clock4. Don't reverse. To reverse CCD Clock 3. To select CCD pixel clamping. To select CCD line clamping.
Offset 1Bh ...................................................................................... Default value = 8'h00 GRAYSET CHANSEL R/W 7 6 5 GRAYSET CHANSEL BGRENB R/W 0 1 0 1 0 1 4 ICGENB 3-0 ICGDLY[3:0] BGRENB R/W ICGENB R/W ICGDLY3 R/W ICGDLY2 R/W ICGDLY1 R/W ICGDLY0 R/W
Select single channel output. Select two channel output. Fast true gray latch is 2 and 3 position. Fast true gray latch is 1 and 2 position. The order is R-G-B. The order of latching A/D data is B-G-R.
0 To disable ICG control. 1 To enable CCD shutter control signal ICG. CCD ICG delay for rising/falling edge.
Offset 1Ch ................................................................................... Default value = 8'h00 CK4MTGL CK3MTGL CK1MTGL CKAREA R/W R/W R/W R/W 7 CK4MTGL 6 CK3MTGL 5 CK1MTGL 4 CKAREA 3 MTLWD 2-0 TGTIME[2:0] MTLWD R/W TGTIME2 R/W TGTIME1 R/W TGTIME0 R/W
0 Disable toggle function in CCD clock 4. 1 Enable toggle function in CCD clock 4. 0 Disable toggle function in CCD clock 3. 1 Enable toggle function in CCD clock 3. 0 Disable toggle function in CCD clock 1 & 2. 1 Enable toggle function in CCD clock 1 &2. 0 This function is disabled. 1 CCD clock speed depends on CKSEL in scan area and DCKSEL in non-scan area. 0 Set the watchdog time-out as WDTIME[3:0]. 1 Set the watchdog time-out as WDTIME[3:0] * 2. CCD line period selection. 000 1*LPERIOD(Reg38,Reg39) 001 2*LPERIOD 010 4*LPERIOD 011 8*LPERIOD 100 16*LPERIOD 101 32*LPERIOD 110 Reserved. 111 Reserved.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 31
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 1Dh ..................................................................................... Default value = 8'h04 CK4LOW R/W CK3LOW R/W CK1LOW R/W TGSHLD4 TGSHLD3 TGSHLD2 TGSHLD1 TGSHLD0 R/W R/W R/W R/W R/W
0 Clock 4 will be high when TG goes high. 1 Clock 4 will be low when TG goes high. 6 CK3LOW 0 Clock 3 will be high when TG goes high. 1 Clock 3 will be low when TG goes high. 5 CK1LOW 0 Clock 1 & 2 will be high when TG goes high. 1 Clock 1 & 2 will be low when TG goes high. 4-0 TGSHLD[4:0] CCD TG shoulder width (in pixel time). Please refer to Reg34. Note: Designers have to program the TGSHLD >= 2 (more than two). Offset 1Eh ..................................................................................... Default value = 8'h20 WDTIME3 WDTIME2 WDTIME1 WDTIME0 LINESEL3 LINESEL2 LINESEL1 LINESEL0 R/W R/W R/W R/W R/W R/W R/W R/W 7-4 WDTIME[3:0] To set watch-dog time. The unit is 30 seconds. 3-0 LINESEL[3:0] To set vertical resolution for CIS or dummy lines for CCD. CIS : LINESEL = 0 full resolution. = 1 1/2 resolution. = 2 1/3 resolution . ..... = 15 1/16 resolution. CCD : LINESEL = 0 no dummy line. = 1 1 dummy line. = 2 2 dummy lines. ..... = 15 15 dummy lines. Note: In contrary to dummy line feature in CCD, for low resolution in CIS, the scanning speed is improved by implementing fast motor moving. Offset 1Fh ...................................................................................... Default value = 8'h00 SCANFED7 SCANFED6 SCANFED5 SCANFED4 SCANFED3 SCANFED2 SCANFED1 SCANFED0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 SCANFED[7:0] Steps number setting for moving to scanning position. Please refer to description of Reg6A Note: 1.it cannot be programmed to logic zero. 2.it can be multiplied by2*STEPTIM Offset 20h ...................................................................................... Default value = 8'h00 BUFSEL7 R/W BUFSEL6 R/W BUFSEL5 R/W BUFSEL4 R/W BUFSEL3 R/W BUFSEL2 R/W BUFSEL1 R/W BUFSEL0 R/W
7 CK4LOW
7-0 BUFSEL[7:0]
To set buffer condition. When buffer is full, scanner will stop and wait for host to read out image data from SDRAM. The valid data count (has not been read) is represented by VALIDWORD (in word). Page 32
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
If VALIDWORD < buffer condition, then the scanner will re-start to scan. Following are the units of this register under various SDRAM size. 16M bits SDRAM : 4k words 64M bits SDRAM : 16k words 128M bits SDRAM : 32K words 256M bits SDRAM : 64K words 512M bits SDRAM : 128K words Offset 21h ...................................................................................... Default value = 8'h00 STEPNO7 R/W STEPNO6 R/W STEPNO5 R/W STEPNO4 R/W STEPNO3 R/W STEPNO2 R/W STEPNO1 R/W STEPNO0 R/W
7-0 STEPNO[7:0]
Steps number of "table one" for the acceleration/deceleration of scanning moving. Please refer to section 6.19 and the descriptions of Reg24 & Reg6A. Note: 1.It cannot be programmed to logic zero. 2.it can be multiplied by2*STEPTIM
Offset 22h ...................................................................................... Default value = 8'h00 FWDSTEP7 FWDSTEP6 FWDSTEP5 FWDSTEP4 FWDSTEP3 FWDSTEP2 FWDSTEP1 FWDSTEP0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 FWDSTEP[7:0] Steps number for forward moving when buffer condition is met. Please refer to section 6.19 and the descriptions of Reg20 & Reg24. Note: 1.It cannot be programmed to logic zero. 2.it can be multiplied by2*STEPTIM Offset 23h ...................................................................................... Default value = 8'h00
BWDSTEP7 BWDSTEP6 BWDSTEP5 BWDSTEP4 BWDSTEP3 BWDSTEP2 BWDSTEP1 BWDSTEP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 BWDSTEP[7:0] Steps number for backward moving when image buffer is full. Please refer to section 6.19 and the descriptions of Reg24. Note: 1.It cannot be programmed to logic zero. 2.it can be multiplied by2*STEPTIM Offset 24h ...................................................................................... Default value = 8'h00 FASTNO7 R/W FASTNO6 R/W FASTNO5 R/W FASTNO4 R/W FASTNO3 R/W FASTNO2 FASTNO1 R/W R/W FASTNO0 R/W
7-0 FASTNO[7:0]
Steps number of "table two" for the acceleration/deceleration when image buffer is full. Please refer to section 6.19 and the descriptions of Reg20. Note: It cannot be programmed to logic zero.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 33
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Buffer full position Speed Reg22 Reg21 Reg21 Time Reg24 Reg24
Reg23 Offset 25h ...................................................................................... Default value = 8'h00 X X X X X X X X LINCNT19 LINCNT18 LINCNT17 LINCNT16 R/W R/W R/W R/W
7-4 RESERVED 3-0 LINCNT[19:16] Scanning lines count specified by designers. Note: It cannot be programmed to logic zero. Offset 26h ...................................................................................... Default value = 8'h00 LINCNT15 LINCNT14 LINCNT13 LINCNT12 LINCNT11 LINCNT10 LINCNT9 R/W R/W R/W R/W R/W R/W R/W 7-0 LINCNT[15:8] Scanning lines count specified by designers. Note: It cannot be programmed to logic zero. Offset 27h ...................................................................................... Default value = 8'h00 LINCNT7 R/W LINCNT6 R/W LINCNT5 R/W LINCNT4 R/W LINCNT3 R/W LINCNT2 R/W LINCNT1 R/W LINCNT0 R/W LINCNT8 R/W
7-0 LINCNT[7:0]
Scanning lines count specified by designers. Note: It cannot be programmed to logic zero.
Offset 28h ...................................................................................... Default value = 8'h00 GMMWRDATA W
GMMWRDATA This port is for designers to write gamma table.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 34
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 29h ................................................................................... Default value = 8'h00 X X X X X X
RAMADDR20 RAMADDR19 RAMADDR18 RAMADDR17 RAMADDR16
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED 4-0 RAMADDR[20:16] SDRAM start address (in word) to access data. The unit is 16 words. Note: The real SDRAM address IRAM_A[24:0]={RAMADDR[20:0] appended by 0000}. Offset 2Ah ...................................................................................... Default value = 8'h00
RAMADDR15 RAMADDR14 RAMADDR13 RAMADDR12 RAMADDR11 RAMADDR10 RAMADDR9 RAMADDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 RAMADDR[15:8] SDRAM start address (in word) to access data. The unit is 16 words. Note: The real SDRAM address IRAM_A[24:0]={RAMADDR[20:0] appended by 0000}. Offset 2Bh ...................................................................................... Default value = 8'h00
RAMADDR7 RAMADDR6 RAMADDR5 RAMADDR4 RAMADDR3 RAMADDR2 RAMADDR1 RAMADDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 RAMADDR[7:0] SDRAM start address (in word) to access data. The unit is 16 words. Note: The real SDRAM address IRAM_A[24:0]={RAMADDR[20:0] appended by 0000}. Offset 2Ch ...................................................................................... Default value = 8'h00 X X X X DPISET13 DPISET12 DPISET11 DPISET10 R/W R/W R/W R/W Set resolution in dpi for average or deletion type.
A. average type : digital average function support 1/2,1/3,1/4,1/5,1/6,1/8,1/10,1/12,1/15. a. 9600 dpi mode CCD:support 4800,3200,2400,1920,1600,1200,960,800,640 dpi. b. 4800 dpi mode CCD:support 2400,1600,1200,960,800,480,400,320 dpi. c. 2400 dpi mode CCD:support 1200,800,600,480,400,300,240,200,160 dpi. d. 1200 dpi mode CCD:support 600,400,300,240,200,150,120,100,80 dpi. e. 600 dpi mode CCD:support 300,200,150,120,100,75,60,50,40 dpi.
DPISET9 R/W
DPISET8 R/W
7-5 RESERVED 4-0 DPISET[13:8]
B. deletion type : 9600,4800,2400,1200 or 600dpi to 1 dpi setting decrement by one dpi. Note: It cannot be programmed to logic zero. Offset 2Dh ...................................................................................... Default value = 8'h00 DPISET7 R/W DPISET6 R/W DPISET5 R/W DPISET4 R/W DPISET3 R/W DPISET2 R/W DPISET1 R/W DPISET0 R/W
7-0 DPISET[7:0]
Set resolution in dpi for average or deletion type.
A. average type : digital average function support 1/2,1/3,1/4,1/5,1/6,1/8,1/10,1/12,1/15. a. 9600 dpi mode CCD:support 4800,3200,2400,1920,1600,1200,960,800,640 dpi. b. 4800 dpi mode CCD:support 2400,1600,1200,960,800,480,400,320 dpi. c. 2400 dpi mode CCD:support 1200,800,600,480,400,300,240,200,160 dpi.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 35
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
d. 1200 dpi mode CCD:support 600,400,300,240,200,150,120,100,80 dpi. e. 600 dpi mode CCD:support 300,200,150,120,100,75,60,50,40 dpi.
B. deletion type : 9600,4800,2400,1200 or 600dpi to 1 dpi setting decrement by one dpi. Note: It cannot be programmed to logic zero. Offset 2Eh ...................................................................................... Default value = 8'h00 BWHI7 R/W BWHI6 R/W BWHI5 R/W BWHI4 R/W BWHI3 R/W BWHI2 R/W BWHI1 R/W BWHI0 R/W
7-0 BWHI[7:0]
High level of Black & White threshold.
Offset 2Fh ...................................................................................... Default value = 8'h00 BWLOW7 BWLOW6 BWLOW5 BWLOW4 BWLOW3 BWLOW2 BWLOW1 BWLOW0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 BWLOW[7:0] BWHI b BWLOW c e Low level of Black & White threshold. d f h i hysteresis width
a
g
a,b,c,g : will be classified as black pixels d,e,f,h,i : will be classified as white pixels Offset 30h ...................................................................................... Default value = 8'h00
STRPIXEL15 STRPIXEL14 STRPIXEL13 STRPIXEL12 STRPIXEL11 STRPIXEL10 STRPIXEL9 STRPIXEL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 STRPIXEL[15:8] The start pixel position of horizontal line (unit : pixel count). STRPIXEL=(TGW+2*TGSHLD)+start pixels number (count from CCD pixel 0) Note: 1.It cannot be programmed to logic zero. 2.If the DPI9600 control bit is set to "1",the STRPIXEL is doubled. Offset 31h ...................................................................................... Default value = 8'h00
STRPIXEL7 STRPIXEL6 STRPIXEL5 STRPIXEL4 STRPIXEL3 STRPIXEL2 STRPIXEL1 STRPIXEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 STRPIXEL[7:0] The start pixel position of horizontal line (unit : pixel count). STRPIXEL=(TGW+2*TGSHLD)+start pixels number (count from CCD pixel 0) Note: 1.It cannot be programmed to logic zero. 2.If the DPI9600 control bit is set to "1",the STRPIXEL is doubled.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 36
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 32h ...................................................................................... Default value = 8'h00
ENDPIXEL15 ENDPIXEL14 ENDPIXEL13 ENDPIXEL12 ENDPIXEL11 ENDPIXEL10 ENDPIXEL9 ENDPIXEL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 ENDPIXEL[15:8] The end pixel position of horizontal line (unit : pixel count). ENDPIXEL=(TGW+2*TGSHLD)+end pixels number (count from CCD pixel 0) Note: 1.It cannot be programmed to logic zero. 2.If the DPI9600 control bit is set to "1",the STRPIXEL is doubled. Offset 33h ...................................................................................... Default value = 8'h00
ENDPIXEL7 ENDPIXEL6 ENDPIXEL5 ENDPIXEL4 ENDPIXEL3 ENDPIXEL2 ENDPIXEL1 ENDPIXEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 ENDPIXEL[7:0] The end pixel position of horizontal line (unit : pixel count). ENDPIXEL=(TGW+2*TGSHLD)+end pixels number (count from CCD pixel 0) Note: 1.It cannot be programmed to logic zero. 2.If the DPI9600 control bit is set to "1",the STRPIXEL is doubled. Offset 34h ...................................................................................... Default value = 8'h00 DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1 DUMMY0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 DUMMY[7:0] The CCD dummy & optical black pixels number (unit : pixel count). Note: It cannot be programmed to logic zero. Reg30,31,32,33 and 34 setting rule. TGSHLD(Reg1D) RGW(Reg17) TGSHLD(Reg1D)
CCD TG
CCD clock CCD pixel no: N-1 N 0 1 For example, start pixel is 65 ,end pixel is 100 and CCD dummy pixel is 64, Then STRPIXEL=(TGW+2*TGSHLD)+65. ENDPIXEL=(TGW+2*TGSHLD)+100. DUMMY =(TGW+2*TGSHLD)+64. 2 3 4
Offset 35h ..................................................................................... Default value = 8'h00 MAXWD24 MAXWD23 MAXWD22 MAXWD21 MAXWD20 MAXWD19 MAXWD18 MAXWD17 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 MAXWD[24:17] Maximum word size per line for ASIC estimation. The unit is 2 words. If available buffer size < MAXWD, then "buffer full" state will be set. The scanner execute backtracking.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 37
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 36h ....................................................................................... Default value = 8'h00 MAXWD16 MAXWD15 MAXWD14 MAXWD13 MAXWD12 MAXWD11 MAXWD10 MAXWD9 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 MAXWD[16:9] Maximum word size per line for ASIC estimation. The unit is 2 words. If available buffer size < MAXWD, then "buffer full" state will be set. The scanner execute backtracking. Offset 37h ....................................................................................... Default value = 8'h00 MAXWD8 MAXWD7 MAXWD6 MAXWD5 MAXWD4 MAXWD3 MAXWD2 MAXWD1 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 MAXWD[8:1] Maximum word size per line for ASIC estimation. The unit is 2 words. If available buffer size < MAXWD, then "buffer full" state will be set. The scanner execute backtracking.
Offset 38h ...................................................................................... Default value = 8'h2A
LPERIOD15 LPERIOD14 LPERIOD13 LPERIOD12 LPERIOD11 LPERIOD10 LPERIOD9 LPERIOD8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 LPERIOD[15:8] Line period (or exposure time) for CCD or CIS. Unit : pixel count Note: It cannot be programmed to logic zero. Offset 39h ...................................................................................... Default value = 8'h30 LPERIOD7 LPERIOD6 LPERIOD5 LPERIOD4 LPERIOD3 LPERIOD2 LPERIOD1 LPERIOD0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 LPERIOD[7:0] Line period (or exposure time) for CCD or CIS. Unit : pixel count Note: It cannot be programmed to logic zero. Offset 3Ah X X X X X X X X X X X X X X
FEWRDATA8
W
7-1 RESERVED 0 FEWRDATA8 This port is for designers to write control register of front-end. Offset 3Bh
FEWRDATA7 FEWRDATA6 FEWRDATA5 FEWRDATA4 FEWRDATA3 FEWRDATA2 FEWRDATA1 FEWRDATA0
W
W
W
W
W
W
W
W
7-0 FEWRDATA[7:0] This port is for designers to write control register of front-end.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 38
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 3Ch RAMWRDATA W
RAMWRDATA This port is for designers to write data into SDRAM.
Offset 3Dh ..................................................................................... Default value = 8'h00 X X X X X X X X FEEDL19 R/W FEEDL18 R/W FEEDL17 R/W FEEDL16 R/W
7-4 RESERVED 3-0 FEEDL[19:16] Steps number of motor moving. Note: It cannot be programmed to logic zero. Offset 3Eh ..................................................................................... Default value = 8'h00 FEEDL15 R/W FEEDL14 R/W FEEDL13 R/W FEEDL12 R/W FEEDL11 R/W FEEDL10 R/W FEEDL9 R/W FEEDL8 R/W
7-0 FEEDL[15:8]
Steps number of motor moving. Note: It cannot be programmed to logic zero.
Offset 3Fh ..................................................................................... Default value = 8'h00 FEEDL7 R/W FEEDL6 R/W FEEDL5 R/W FEEDL4 R/W FEEDL3 R/W FEEDL2 R/W FEEDL1 R/W FEEDL0 R/W
7-0 FEEDL[7:0]
Steps number of motor moving. Note: It cannot be programmed to logic zero.
Offset 40h DOCSNR R 7 6 5 4 3 ADFSNR COVERSNR CHKVER R R R DOCJAM HISPDFLG MOTMFLG DATAENB R R R R
DOCSNR ADFSNR COVERSNR CHKVER DOCJAM
2 HISPDFLG 1 MOTMFLG 0 DATAENB
Respond to document sensor status for ADF function. Respond to ADF sensor status for ADF function. Respond to cover sensor status for ADF function. It is fixed to `1' to indicate that the value in Reg00 is valid. Respond to document feeding status for ADF function. 0 No jam happened. 1 Document jammed. 0 Motor is not in high-speed moving. 1 Motor is in high-speed moving. 0 Motor is stop. 1 Motor is moving. 0 Scanner is in command mode. Designers can access other data in SDRAM rather than image data. 1 Scanner is in scanning mode. Designers can only read the image data. Page 39
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 41h PWRBIT BUFEMPTY FEEDFSH SCANFSH HOMESNR LAMPSTS R R R R R R 7 PWRBIT FEBUSY MOTORENB R R
6 BUFEMPTY 5 FEEDFSH 4 SCANFSH 3 HOMESNR 2 LAMPSTS 1 FEBUSY 0 MOTORENB
To indicate power status. If it is reset, the power had been turned off. Power on initial process will set PWRBIT to 0. This bit will have the same value as bit 4 of Reg06 except for it's read only. 0 The image buffer is not empty. 1 The image buffer is empty. 0 Motor feeding is not finished. 1 Motor feeding is finished. 0 Scanning is not finished. 1 Scanning is finished. 0 Home sensor is on (is not located in home position). 1 Home sensor is off (located in home position). 0 Lamp is off. 1 Llamp is on. 0 Front end is ready for read/write operations. 1 Front end is busy and can not perform read/write operations. 0 Motor is not operation. 1 Motor is operation.
Offset 42h ....................................................................................... Default value = 8'h00
VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD
24 R
23 R
22 R
21 R
20 R
19 R
18 R
17 R
7-0 VALIDWORD [24:17]
The available image data stored in SDRAM for host to read. The unit is in two words.
Offset 43h ....................................................................................... Default value = 8'h00
VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD
16 R
15 R
14 R
13 R
12 R
11 R
10 R
9 R
7-0 VALIDWORD [16:9]
The available image data stored in SDRAM for host to read. The unit is in two words.
Offset 44h ....................................................................................... Default value = 8'h00
VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD VALIDWORD
8 R
7 R
6 R
5 R
4 R
3 R
2 R
1 R
7-0 VALIDWORD [8:1]
The available image data stored in SDRAM for host to read. The unit is in two words.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 40
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 45h RAMRDDATA R
RAMRDDATA
This port for designers to read data from SDRAM.
Offset 46h X X X X X X X X X X X X X X
FERDDATA8
R
7-1 RESERVED 0 FERDDATA8 Offset 47h
This port is for designers to read control register from front-end.
FERDDATA7 FERDDATA6 FERDDATA5 FERDDATA4 FERDDATA3 FERDDATA2 FERDDATA1 FERDDATA0
R
R
R
R
R
R
R
R
7-0 FERDDATA[7:0] This port is for designers to read control register from front-end. Offset 48h ....................................................................................... Default value = 8'h00 X X X X X X X X FEDCNT19 FEDCNT18 FEDCNT17 FEDCNT16 R R R R
7-4 RESERVED 3-0 FEDCNT[19:16] Steps number which motor has moved. For example, after setting the moving steps number (Reg 3D, 3E 3F) and execute the moving command (Reg 0F), designers can get steps number which has been moved via these registers. It can be reset to by FULLSTP command.
Offset 49h ....................................................................................... Default value = 8'h00 FEDCNT15 FEDCNT14 FEDCNT13 FEDCNT12 FEDCNT11 FEDCNT10 FEDCNT9 FEDCNT8 R R R R R R R R 7-0 FEDCNT[15:8] Steps number which motor has moved. For example, after setting the moving steps number (Reg 3D, 3E 3F) and execute the moving command (Reg 0F), designers can get steps number which has been moved via these registers .It can be reset to by FULLSTP command. Offset 4Ah ....................................................................................... Default value = 8'h00 FEDCNT7 FEDCNT6 FEDCNT5 FEDCNT4 FEDCNT3 FEDCNT2 FEDCNT1 FEDCNT0 R R R R R R R R 7-0 FEDCNT[7:0] Steps number which motor has moved. For example, after setting the moving steps number (Reg 3D, 3E 3F) and execute the moving command (Reg 0F), designers can get steps number which has been moved via these registers.It can be reset to by FULLSTP command. Page 41
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 4Bh ....................................................................................... Default value = 8'h00 X X X X X X X X
SCANCNT19 SCANCNT18 SCANCNT17 SCANCNT16
R
R
R
R
7-4 RESERVED 3-0 SCANCNT[19:16] Line number which scanner has finished. For example, after setting the line number (Reg 25, 26 27) and execute the scanning enable (bit 0 of Reg 01), designers can get line number which has been finished via these registers. Offset 4Ch ....................................................................................... Default value = 8'h00
SCANCNT15 SCANCNT14 SCANCNT13 SCANCNT12 SCANCNT11 SCANCNT10 SCANCNT9 SCANCNT8
R
R
R
R
R
R
R
R
7-0 SCANCNT[15:8] Line number which scanner has finished. For example, after setting the line number (Reg 25, 26 27) and execute the scanning enable (bit 0 of Reg 01), designers can get line number which has been finished via these registers. Offset 4Dh ....................................................................................... Default value = 8'h00
SCANCNT7 SCANCNT6 SCANCNT5 SCANCNT4 SCANCNT3 SCANCNT2 SCANCNT1 SCANCNT0
R
R
R
R
R
R
R
R
7-0 SCANCNT[7:0] Line number which scanner has finished. For example, after setting the line number (Reg 25, 26 27) and execute the scanning enable (bit 0 of Reg 01), designers can get line number which has been finished via these registers. Offset 4Eh GMMRDDATA R
GMMRDDATA This port is for designers to read gamma table back.
Offset 4Fh X X 7-5 RESERVED 4 ROMBSY 3 LCMBSY 2 TX232BSY 1 RX232BSY 0 RXREADY
X X
X X 0 1 0 1 0 1 0 1 0
ROMBSY R
LCMBSY TX232BSY RX232BSY RXREADY R R R R
EEPROM is ready for access. EEPROM (93C46) is busy and can not be accessed. LCM interface is ready for access. LCM interface is busy and can not be accessed. RS232 transmitter is ready for access. RS232 transmitter is busy and can not be accessed. RS232 receiver is ready for access. RS232 receiver is busy and can not be accessed. The receiving has not been completed. Page 42
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
1 Has received data number specified in Reg 88 from RS232. Offset 50h ........................................................................................ Default value = 8'h00 X X 7-6 RESERVED 5-0 FERDA[5:0] X X FERDA5 R/W FERDA4 R/W FERDA3 R/W FERDA2 R/W FERDA1 R/W FERDA0 R/W
Address of control register of front-end in read operation. Before reading control register of front-end (Reg 46, 47), designers have to specify address of the control register by writing address to this port.
Offset 51h ........................................................................................ Default value = 8'h00 X X X X FEWRA5 R/W FEWRA4 R/W FEWRA3 R/W FEWRA2 R/W FEWRA1 R/W FEWRA0 R/W
7-6 RESERVED 5-0 FEWRA[5:0]
Address of control register of front-end in write operation. Before writing control register of front-end (Reg 3A, 3B), designers have to specify address of the control register by writing address to this port.
Offset 52h ........................................................................................ Default value = 8'h00 X X 7-5 RESERVED 4-0 RHI[4:0] X X X X RHI4 R/W RHI3 R/W RHI2 R/W RHI1 R/W RHI0 R/W
The latch point for high-byte of R channel of AFE in every pixel. For example, if a system is designed to have 12 clocks/pixel, and designer wants to latch the high-byte of R channel at 1'st clock in every pixel, designer has to fill `00001' to RHI [4:0].
Offset 53h ........................................................................................ Default value = 8'h00 X X 7-5 RESERVED 4-0 RLOW[4:0] X X X X RLOW4 R/W RLOW3 R/W RLOW2 R/W RLOW1 R/W RLOW0 R/W
The latch point for low-byte of R channel of AFE in every pixel For example, if a system is designed to have 12 clocks/pixel, and designer wants to latch the high-byte of R channel at 1'st clock in every pixel, designer has to fill `00001' to RHI [4:0].
Offset 54h ........................................................................................ Default value = 8'h00 X X 7-5 RESERVED 4-0 GHI[4:0] X X X X GHI4 R/W GHI3 R/W GHI2 R/W GHI1 R/W GHI0 R/W
The latch point for high-byte of G channel of AFE in every pixel.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 43
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 55h ........................................................................................ Default value = 8'h00 X X 7-5 RESERVED 4-0 GLOW[4:0] X X X X GLOW4 R/W GLOW3 R/W GLOW2 R/W GLOW1 R/W GLOW0 R/W
The latch point for low-byte of G channel of AFE in every pixel.
Offset 56h ........................................................................................ Default value = 8'h00 X X 7-5 RESERVED 4-0 BHI[4:0] X X X X BHI4 R/W BHI3 R/W BHI2 R/W BHI1 R/W BHI0 R/W
The latch point for high-byte of B channel of AFE in every pixel.
Offset 57h ........................................................................................ Default value = 8'h00 X X X X X X BLOW4 R/W BLOW3 R/W BLOW2 R/W BLOW1 R/W BLOW0 R/W
7-5 RESERVED 4-0 BLOW[4:0] The latch point for low-byte of B channel of AFE in every pixel. (1). Color, gray or line-art : 12 clocks (phase)/pixel mode 0 1 2 34 56 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
R[15:8] R[7:0] G[15:8] G[7:0] B[15:8]
B[7:0]
R[15:8] R[7:0]
G[15:8] G[7:0]
B[15:8]
RHI = 01H RLOW = 03H GHI = 05H GLOW = 07H BHI = 09H BLOW = 11H Note: 16 clocks (phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode. Offset 58h ........................................................................................ Default value = 8'h00 VSMP4 R/W VSMP3 R/W VSMP2 R/W VSMP1 R/W VSMP0 R/W VSMPW2 R/W VSMPW1 R/W VSMPW0 R/W
7-3 VSMP[4:0] 2-0 VSMPW[2:0]
Rising edge position of image sampling for AFE. Pulse width of image sampling.
(1). Color, gray or line-art : 12 clocks (phase)/pixel mode 5 AFE 67 VSMP Reg58=52H : VSMP[4:0]=10H VSMPW[2:0]=2H Note: 16 clocks (phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode. (c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 44 8 9 10 11 0 1 2 34 5 67 8 9 10 11 01 234
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 59h ........................................................................................ Default value = 8'h00 BSMP4 R/W BSMP3 R/W BSMP2 R/W BSMP1 R/W BSMP0 R/W BSMPW2 R/W BSMPW1 R/W BSMPW0 R/W
7-3 BSMP[4:0] 2-0 BSMPW[2:0]
Rising edge position of dark voltage sampling for AFE. Pulse width of dark voltage sampling.
(1). Color, gray or line-art : 12 clocks (phase)/pixel mode 5 67 8 9 10 11 0 1 2 34 5 67 8 9 10 11 01 234
AFE
BSMP Reg59=52H : BSMP[4:0]=10H BSMPW[2:0]=2H Note: 16 clocks (phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode.
Offset 5Ah ..................................................................................... Default value = 8'h00
ADCLKINV
R/W
RLCSEL R/W
CDSREF1 R/W
CDSREF0 R/W
RLC3 R/W
RLC2 R/W
RLC1 R/W
RLC0 R/W
7 ADCLKINV 6 RLCSEL 5-4 CDSREF[1:0] 3-0 RLC[3:0]
0 ADC clock in not reversed. 1 ADC clock is reversed. 0 Do not select. 1 Select reset level clamp on a pixel-by-pixel basis. Front-end CDS reference for line rate scanning type. Front-end RLC for line rate scanning type.
Offset 5Bh ..................................................................................... Default value = 8'h00
X X
MTRTBL R/W
GMMADDR13 GMMADDR12 GMMADDR11 GMMADDR10 GMMADDR9 GMMADDR8
R/W
R/W
R/W
R/W
R/W
R/W
0 To write gamma tables address by GMMADDR[12:0] 1 To write motor tables address by GMMADDR[12:0] 5-0 GMMADDR[13:8] Start address for downloading gamma or motor tables (in word) Offset 5Ch ..................................................................................... Default value = 8'h00
GMMADDR7 GMMADDR6 GMMADDR5 GMMADDR4 GMMADDR3 GMMADDR2 GMMADDR1 GMMADDR0
7 RESERVED 6 MTRTBL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 GMMADDR[7:0] Start address for downloading gamma or motor tables (in word) Offset 5Dh ..................................................................................... Default value = 8'h00 HISPD7 R/W HISPD6 R/W HISPD5 R/W HISPD4 R/W HISPD3 R/W HISPD2 R/W HISPD1 R/W HISPD0 R/W
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 45
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
7-0 HISPD[7:0] To change of the speed of motor during moving Note: It cannot be programmed to logic zero.
Offset 5Eh ..................................................................................... Default value = 8'h00 DECSEL2 R/W DECSEL1 R/W DECSEL0 STOPTIM4 STOPTIM3 STOPTIM2 STOPTIM1 STOPTIM0 R/W R/W R/W R/W R/W R/W
7-5 DECSEL[2:0]
Deceleration steps number after touching home sensor. 000 1 steps deceleration 001 2 steps deceleration 010 4 steps deceleration 011 8 steps deceleration 100 16 steps deceleration 101 32 steps deceleration 110 64 steps deceleration 111 128 steps deceleration 4-0 STOPTIM[4:0] Stop time between forward and backward direction in backtracking. Note: In ASIC simulation process, STOPTIM has to be set to tgtime=6,7. It cannot be programmed to logic zero. Offset 5Fh ...................................................................................... Default value = 8'h00
FMOVDEC7 FMOVDEC6 FMOVDEC5 FMOVDEC4 FMOVDEC3 FMOVDEC2 FMOVDEC1 FMOVDEC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FMOVDEC[7:0] Deceleration steps in table 5 for auto-go-home. Note: 1.It cannot be programmed to logic zero. 2.It can be multiplied by 2 *STEPTIM Offset 60h ...................................................................................... Default value = 8'h00 X X X X X X Z1MOD20 Z1MOD19 Z1MOD18 Z1MOD17 Z1MOD16 R/W R/W R/W R/W R/W
7-5 RESERVED 4-0 Z1MOD[20:16] "remainder value" of MOD operation in acceleration/deceleration tables. ASIC calculate the moving time by MOD operation when buffer-full occurs. Note: It should be less than LPERIOD. Offset 61h ...................................................................................... Default value = 8'h00 Z1MOD15 Z1MOD14 Z1MOD13 Z1MOD12 Z1MOD11 Z1MOD10 Z1MOD7 R/W R/W R/W R/W R/W R/W R/W 7-0 Z1MOD[15:8] Z1MOD8 R/W
"remainder value" of MOD operation in acceleration/deceleration tables. ASIC calculate the moving time by MOD operation when buffer-full occurs. Note: It should be less than LPERIOD.
Offset 62h ...................................................................................... Default value = 8'h00 Z1MOD7 R/W Z1MOD6 R/W Z1MOD5 Z1MOD4 R/W R/W Z1MOD3 R/W Z1MOD2 R/W Z1MOD1 R/W Z1MOD0 R/W Page 46
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
7-0 Z1MOD[7:0]
"remainder value" of MOD operation in acceleration/deceleration tables. ASIC calculate the moving time by MOD operation when buffer-full occurs. Note: It should be less than LPERIOD.
Offset 63h ...................................................................................... Default value = 8'h00 X X X X X X Z2MOD20 Z2MOD19 Z2MOD18 Z2MOD17 Z2MOD16 R/W R/W R/W R/W R/W
7-5 RESERVED 7-0 Z2MOD[20:16] "remainder value" of MOD operation in acceleration/deceleration tables. ASIC calculate the moving time by MOD operation when scanner start to move. Note: It should be less than LPERIOD. Note:for ACDCDIS=1,designer must subtract any small offset value from Z2MOD to solve the first time start/stop motor position problem. Offset 64h ...................................................................................... Default value = 8'h00 Z2MOD15 Z2MOD14 Z2MOD13 Z2MOD12 Z2MOD11 Z2MOD10 R/W R/W R/W R/W R/W R/W 7-0 Z2MOD[15:8] Z2MOD9 R/W Z2MOD8 R/W
"remainder value" of MOD operation in acceleration/deceleration tables. ASIC calculate the moving time by MOD operation when scanner start to move. Note: It should be less than LPERIOD. solve the first time start/stop motor position problem.
Note:for ACDCDIS=1,designer must subtract any small offset value from Z2MOD to
Offset 65h ...................................................................................... Default value = 8'h00 Z2MOD7 R/W Z2MOD6 R/W Z2MOD5 R/W Z2MOD4 R/W Z2MOD3 R/W Z2MOD2 R/W Z2MOD1 R/W Z2MOD0 R/W
7-0 Z2MOD[7:0]
"remainder value" of MOD operation in acceleration/deceleration tables. ASIC calculate the moving time by MOD operation when scanner start to move. Note: It should be less than LPERIOD. solve the first time start/stop motor position problem.
Note:for ACDCDIS=1,designer must subtract any small offset value from Z2MOD to
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 47
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
(1). Two table moving : speed Scanning position buffer full position
b a c
d
time
(2). One table moving : speed Scanning position buffer full position
b a
d c time
{a+(b-1)} mode LPERIOD = Z2MOD {c+(d-1)} mode LPERIOD = Z1MOD For example, c (STEPNO = 4 steps for table 1) = 60H,48H,30H,18H d (FWDSTEP = 3 steps for moving) = 18H,18H,18H LPERIOD = 30H Then Z1MOD = {(60H + 48H + 30H + 18H) + (18H +18H )} MOD {30H} = 00H Note: If MCNTSET[1:0]=01 or 10 or 11,then (each step curve value + 1)/VCNT. VCNT= system clocks per pixel / (MCNTSET+1). Offset 66h ........................................................................................ Default value = 8'h00 PHFREQ7 R/W PHFREQ6 R/W PHFREQ5 R/W PHFREQ4 R/W PHFREQ3 R/W PHFREQ2 R/W PHFREQ1 R/W PHFREQ0 R/W
7-0 PHFREQ[7:0]
PWM frequency for motor phase of unipolar motors Frequency: (system clock frequency)/[(PHFREQ+1)*4
Offset 67h ...................................................................................... Default value = 8'h7F STEPSEL1 STEPSEL0 MTRPWM5 MTRPWM4 MTRPWM3 MTRPWM2 MTRPWM1 MTRPWM0 R/W R/W R/W R/W R/W R/W R/W R/W
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 48
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
7-6 STEPSEL[1:0] For type selection of table one, table two and table three in scanning mode. (1) For bipolar motors: 00 Full step (for 1939, 1940, 2916, 6219, 3955, 3967). 01 Half step (for 1939, 1940, 2916, 6219, 3955, 3967). 10 Quarter step (for 2916, 6219, 3955, 3967). 11 Eighth step (for 3955, 3967). (2) For unipolar motors: 00 Two-phase-on full step. 01 Half step. 10 Reserved. 11 Single-phase-on full step. 5-0 MTRPWM[5:0] PWM duty cycle selection of table one, table two and table three of motor phase of unipolar motors in scanning mode. MTRPWM = 0 1/64 duty = 1 2/64 duty = 2 3/64 duty ...... = 63 64/64 duty Note: If PHFREQ < 0FH,then PWM setting must < (PHFREQ+1)*4 Offset 68h ...................................................................................... Default value = 8'h7F FSTPSEL1 FSTPSEL0 FASTPWM5 FASTPWM4 FASTPWM3 FASTPWM2 FASTPWM1 FASTPWM0 R/W R/W R/W R/W R/W R/W R/W R/W 7-6 FSTPSEL[1:0] For type selection of table four and table five in command mode. (1) For bipolar motors: 00 Full step (for 1939, 1940, 2916, 6219, 3955, 3967). 01 Half step (for 1939, 1940, 2916, 6219, 3955, 3967). 10 Quarter step (for 2916, 6219, 3955, 3967). 11 Eighth step (for 3955, 3967). (2) For unipolar motors: 00 Two-phase-on full step. 01 Half step. 10 Reserved. 11 Single-phase-on full step. 5-0 FASTPWM[5:0] PWM duty cycle selection of table four and table five of motor phase of unipolar motors in scanning mode. FASTPWM = 0 1/64 duty = 1 2/64 duty = 2 3/64 duty ...... = 63 64/64 duty Note: If PHFREQ < 0FH,then PWM setting must < (PHFREQ+1)*4 Offset 69h ........................................................................................ Default value = 8'h00 FSHDEC7 R/W FSHDEC6 R/W FSHDEC5 R/W FSHDEC4 R/W FSHDEC3 R/W FSHDEC2 FSHDEC1 R/W R/W FSHDEC0 R/W
7-0 FSHDEC[7:0]
Deceleration steps after scanning finished (table three).
Note: It cannot be programmed to logic zero.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 49
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 6Ah ...................................................................................... Default value = 8'h00 FMOVNO7 FMOVNO6 FMOVNO5 FMOVNO4 FMOVNO3 FMOVNO2 FMOVNO1 FMOVNO0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 FMOVNO[7:0] Acceleration/deceleration steps for fast moving (table four). Note: 1.It cannot be programmed to logic zero. 2.It can be multiplied by 2* STEPTIM (1). Two table type: speed Scanning position scan finished Reg3D,3E,3F Reg6A Reg1F Reg25,26,27 Reg69
Reg21
Reg5E[7:5] Reg5F
Reg5E[4:0] Go home
Reg6A
Length
(2). One table type: speed Scanning position scan finished
Reg3D,3E,3F Reg21
Reg25,26,27 Reg69 Length
Reg5F Reg5E[7:5] Go home
Reg6A
Offset 6Bh ...................................................................................... Default value = 8'h00
MULTFILM
R/W
GPOM13 R/W
GPOM12 R/W
GPOM11 R/W
GPOCK4 R/W
GPOCP R/W
GPOLEDB R/W
GPOADF R/W
7 MULTFILM
6 GPOM 13
0 Disable multi-film scanning mode. 1 Enable multi-film scanning mode. Motor power will not be turned off in this mode. 0 Select GPIO13 as general purpose I/O. 1 Select GPIO13 as V-ref control of bipolar motor driver IC to control Imax.
5 GPOM12
0 Select GPIO12 as general purpose I/O. 1 Select GPIO12 as V-ref control of bipolar motor driver IC to control Imax. 4 GPOM11 0 Select GPIO11 as general purpose I/O.. 1 Select GPIO11 as V-ref control of bipolar motor driver IC to control Imax. Note: GPIO12: 1. Add a pull up resistor on GPIO12 will indicate ASIC to turn on lamp power in power-on initial state. This behavior is independent to setting of GPOM12. (c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 50
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
2. Add a pull down resistor on GPIO12 will indicate ASIC to turn off lamp power in power-on initial state. This behavior is independent to setting of GPOM12. 3. This pin can control bipolar motor driver IC (2916,6219,3955 or 3967) Vref for controlling Imax current when GPOM12 is set to `1'. GPIO11: This pin can control bipolar motor driver IC (2916,6219,3955 or 3967) Vref for controlling Imax current when GPOM11 is set to `1'. GPOCK4 0 Select pin62 as CCD_CK4X 1 Select CCD_CK4X as GPO33 GPOCP 0 Select this pin68 as CCD_CPX. 1 CCD_CPX as GPO32. GPOLEDB 0 Select this pin as LED_B for CIS. 1 Select LED_B as GPO28. GPOADF 0 Select normal function for GPIO6 and GPO28. 1 Select GPIO6 as motor STEP output of 3967 and GPO28(LED_B) as DIR output of 3967.
3 2 1 0
Offset 6Ch ...................................................................................... Default value = 8'h00 GPIO16 R/W GPIO15 R/W GPIO14 R/W GPIO13 R/W GPIO12 R/W GPIO11 R/W GPIO10 R/W GPIO9 R/W
7-0 GPIO[16:9]
GPIO16~9 input/output ports
Offset 6Dh ...................................................................................... Default value = 8'h00 GPIO8 R/W GPIO7 R/W GPIO6 R/W GPIO5 R/W GPIO4 R/W GPIO3 R/W GPIO2 R/W GPIO1 R/W
7-0 GPIO[8:1]
GPIO8~1 input/output ports
Offset 6Eh ...................................................................................... Default value = 8'h00 GPOE16 R/W GPOE15 R/W GPOE14 R/W GPOE13 R/W GPOE12 R/W GPOE11 R/W GPOE10 R/W GPOE9 R/W
7-0 GPOE[16:9]
Select directions of GPIO16~9 ports. They can be set to different values independently. 0 Set as input port. 1 Set as output port.
Offset 6Fh ...................................................................................... Default value = 8'h00 GPOE8 R/W GPOE7 R/W GPOE6 R/W GPOE5 R/W GPOE4 R/W GPOE3 R/W GPOE2 R/W GPOE1 R/W
7-0 GPOE[8:1]
Select directions of GPIO8~1 ports. They can be set to different values independently. 0 Set as input port. 1 Set as output port.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 51
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 70h ....................................................................................... Default value = 8'h06 X X 7-5 RESERVED 4-0 RSH[4:0] X X X X RSH4 R/W RSH3 R/W RSH2 R/W RSH1 R/W RSH0 R/W
Rising edge position of CCD RS.
Offset 71h ....................................................................................... Default value = 8'h08 X X X X X X RSL4 R/W RSL3 R/W RSL2 R/W RSL1 R/W RSL0 R/W
7-5 RESERVED 4-0 RSL[4:0] Falling edge position of CCD RS. (1) Color, gray or line-art: 12 clocks(phase)/pixel 0 1 2 3 45 67 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
CCD RS : RSH=08H RSL=0BH Note: 16 clocks(phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode. Offset 72h ....................................................................................... Default value = 8'h08 X X 7-5 RESERVED 4-0 CPH[4:0] X X X X CPH4 R/W CPH3 R/W CPH2 R/W CPH1 R/W CPH0 R/W
Rising edge position of CCD CP.
Offset 73h ...................................................................................... Default value = 8'h0A X X X X X X CPL4 R/W CPL3 R/W CPL2 R/W CPL1 R/W CPL0 R/W
7-5 RESERVED 4-0 CPL[4:0] Falling edge position of CCD CP. (1) Color, gray or line-art: 12 clocks(phase)/pixel 5 6 7 8 9 10 11 0 1 2 3 45 6 7 8 9 10 11 0 1 23 4
CCD CP : CPH=0AH CPL=01H Note: 16 clocks(phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 52
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 74h ........................................................................................ Default value = 8'h00 X X X X X X X X X X X X CK1MAP17 CK1MAP16 R/W R/W
7-2 RESERVED 1-0 CK1MAP[17:16] Bits mapping setting for CCD clock 1 or 2. Offset 75h ........................................................................................ Default value = 8'h00 CK1MAP15 CK1MAP14 CK1MAP13 CK1MAP12 CK1MAP11 CK1MAP10 CK1MAP9 CK1MAP8 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 CK1MAP[15:8] Bits mapping setting for CCD clock 1 or 2. Offset 76h ........................................................................................ Default value = 8'h00 CK1MAP7 CK1MAP6 CK1MAP5 CK1MAP4 CK1MAP3 CK1MAP2 CK1MAP1 CK1MAP0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 CK1MAP[7:0] Bits mapping setting for CCD clock 1 or 2. Offset 77h ........................................................................................ Default value = 8'h00 X X X X X X X X X X X X CK3MAP17 CK3MAP16 R/W R/W
7-2 RESERVED 1-0 CK3MAP[17:16] Bits mapping setting for CCD clock 3. Offset 78h ........................................................................................ Default value = 8'h00 CK3MAP15 CK3MAP14 CK3MAP13 CK3MAP12 CK3MAP11 CK3MAP10 CK3MAP9 CK3MAP8 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 CK3MAP[15:8] Bits mapping setting for CCD clock 3. Offset 79h ........................................................................................ Default value = 8'h00 CK3MAP7 CK3MAP6 CK3MAP5 CK3MAP4 CK3MAP3 CK3MAP2 CK3MAP1 CK3MAP0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 CK3MAP[7:0] Bits mapping setting for CCD clock 3. Offset 7Ah ..................................................................................... Default value = 8'h00 X X 7-2 RESERVED X X X X X X X X X X CK4MAP17 CK4MAP16 R/W R/W
1-0 CK4MAP[17:16] Bits mapping setting for CCD clock 4.
(c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 53
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 7Bh ........................................................................................ Default value = 8'h00 CK4MAP15 CK4MAP14 CK4MAP13 CK4MAP12 CK4MAP11 CK4MAP10 CK4MAP9 CK4MAP8 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 CK4MAP[15:8] Bits mapping setting for CCD clock 4. Offset 7Ch ..................................................................................... Default value = 8'h00 CK4MAP7 CK4MAP6 CK4MAP5 CK4MAP4 CK4MAP3 CK4MAP2 CK4MAP1 CK4MAP0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 CK4MAP[7:0] Bits mapping setting for CCD clock 4. Offset 7Dh ..................................................................................... Default value = 8'h00 CK1NEG R/W CK3NEG R/W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CK4NEG R/W RSNEG R/W CPNEG R/W BSMPNEG VSMPNEG R/W R/W DLYSET R/W
7 CK1NEG 6 CK3NEG 5 CK4NEG 4 RSNEG 3 CPNEG 2 BSMPNEG 1 VSMPNEG 0 DLYSET
CCD clock1,clock2 output are synchronized with rising edge of system clock. CCD clock1 & clock2 output are synchronized with falling edge of system clock.
CCD clock3 output is synchronized with rising edge of system clock. CCD clock3 output is synchronized with falling edge of system clock. CCD clock4 output is synchronized with rising edge of system clock. CCD clock4 output is synchronized with falling edge of system clock. CCD RS output is synchronized with rising edge of system clock. RS output is synchronized with falling edge of system clock. CCD CP output is synchronized with rising edge of system clock. CCD CP output is synchronized with falling edge of system clock. AFE video sample output is synchronized with rising edge of system clock. AFE video sample output is synchronized with falling edge of system clock. AFE dark sample output is synchronized with rising edge of system clock. AFE dark sample output is synchronized with falling edge of system clock. The function is disabled. To enable VSMP and BSMP to delay output by 8.33ns unit. Please refer to Reg 7F.
Offset 7Eh ..................................................................................... Default value = 8'h00 GPOLED25 GPOLED24 GPOLED23 GPOLED22 GPOLED21 GPOLED10 GPOLED9 GPOLED8 R/W R/W R/W R/W R/W R/W R/W R/W 7 GPOLED25 6 GPOLED24 5 GPOLED23 4 GPOLED22 3 GPOLED21 0 1 0 1 0 1 0 1 0 1 Set GPIO25 as general purpose I/O. Set GPIO25 as LED output. Set GPIO24 as general purpose I/O. Set GPIO24 as LED output. Set GPIO23 as general purpose I/O. Set GPIO23 as LED output. Set GPIO22 as general purpose I/O. Set GPIO22 as LED output. Set GPIO21 as general purpose I/O. Set GPIO21 as LED output. Page 54
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
2 GPOLED10 1 GPOLED9 0 GPOLED8 0 1 0 1 0 1 Set GPIO10 as general purpose I/O. Set GPIO10 as LED output. Set GPIO9 as general purpose I/O. Set GPIO9 as LED output. Set GPIO8 as general purpose I/O. Set GPIO8 as LED output.
Offset 7Fh ....................................................................................... Default value = 8'h00
BSMPDLY1 BSMPDLY0 VSMPDLY1 VSMPDLY0 LEDCNT3 LEDCNT2 LEDCNT1 LEDCNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-6 BSMPDLY[1:0] BSMP output delay. 00 No delay. 01 Delay 8.33ns 10 Delay 16.67ns 11 Delay 25ns. 5-4 VSMPDLY[1:0] VSMP output delay. 00 No delay. 01 Delay 8.33ns 10 Delay 16.67ns 11 Delay 25ns. 3-0 LEDCNT[1:0] LED blinking period = (LEDCNT)*(100ms on + 100ms off). LED will not blink if LEDCNT=0. Offset 80h ....................................................................................... Default value = 8'h00 VRHOME1 VRHOME0 VRMOVE1 VRMOVE0 VRBACK1 VRBACK0 VRSCAN1 VRSCAN0 R/W R/W R/W R/W R/W R/W R/W R/W 7-6 5-4 3-2 1-0 VRHOME[1:0] VRMOVE[1:0] VRBACK[1:0] VRSCAN[1:0] Vref. of the motor driver IC for go-home moving. Vref. of the motor driver IC for fast forward moving. Vref. of the motor driver IC for backward moving when the image buffer is full. Vref. of the motor driver IC forward scanning moving.
Offset 81h ....................................................................................... Default value = 8'h00 X X X X set the data types for downloading data. X X
LOADSET4 LOADSET3 LOADSET2 LOADST1 LOADSET0
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED 4-0 LOADSET[4:0]
Offset 82h ....................................................................................... Default value = 8'h00 CONTB3 R/W CONTB2 R/W CONTB1 R/W CONTB0 R/W CONTA3 R/W CONTA2 R/W CONTA1 R/W CONTA0 R/W
7-4 CONTB[7:4] 3-0 CONTA [3:0]
Set flow control counter mode (count method) for flatbed Set flow control counter mode (count method) for ADF Page 55
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 83h ....................................................................................... Default value = 8'h00 IMGSET7 R/W IMGSET6 R/W IMGSET5 R/W IMGSET4 R/W IMGSET3 R/W IMGSET2 R/W IMGSET1 R/W IMGSET0 R/W
7-0 IMGSET[7:0]
Set flow-control to control image process and motor controls.
Offset 84h ....................................................................................... Default value = 8'h00 PACK1 R/W 7-6 5-0 PACK0 R/W
PACKCNT5 PACKCNT4 PACKCNT3 PACKCNT2 PACKCNT1 PACKCNT0
R/W
R/W
R/W
R/W
R/W
R/W
PACK[7:6] Set data packing methods. PACKCNT [5:0] Set packing count.
Offset 87h ....................................................................................... Default value = 8'h00 X X YENB R/W YBIT R/W
ACYCNRLC ENOFFSET LEDADD
R/W
R/W
R/W
CK4ADC AUTOCONF R/W R/W
0 Disable PH_Y output of the YBIT. 1 Enable PH_Y output of the YBIT to improve half-step operation of motor control. 5 YBIT Output port of PH_Y control signal. 4 ACYCNRLC 0 Disable this function. 1 Generate RLC/ACYC pulse through BSMP pin to trigger WM8199 auto-cycling for line-by-line color scanning. 3 ENOFFSET 0 To disable this function. 1 To select automatic offset configuration for CIS color scanning. 2 LEDADD 0 Normal gray by controlling CIS single color LED array. 1 Enable true gray weighting in CIS by separately controlling the exposure times of R, G, B LED array. Please refer to Reg 10~15. 1 CK4ADC 0 Select MCLK (ADCCLK) to output default timing for specified AFE. 1 Select MCLK (ADCCLK) pin to output according to pattern defined by CK4MAP (Reg 7A,7B,7C). 0 AUTOCONF 0 To disable these functions. 1 Enable automatic channel switching and offset configuration for CIS color scanning. Note: If YBIT=1, then YENB=1 => PH_Y=1; YENB=0 => PH_Y=0. If YBIT=0, then YENB=1 => PH_Y=0; YENB=0 => PH_Y=1. Offset 88h ....................................................................................... Default value = 8'h00 X X X X X X RDNUM4 R/W RDNUM3 R/W RDNUM2 R/W RDNUM1 R/W RDNUM0 R/W
7 RESERVED 6 YENB
7-5 RESERVED 4-0 RDNUM[4:0]
Set the receiving length in bytes of RS232 interface.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 56
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 89h RS232WD7 RS232WD6 RS232WD5 RS232WD4 RS232WD3 RS232WD2 RS232WD1 RS232WD0 7-0 RS232WD[7:0] This port is for designers to write data to RS232 interface. Offset 8Ah RS232RD7 RS232RD6 RS232RD5 RS232RD4 RS232RD3 RS232RD2 RS232RD1 RS232RD0 7-0 RS232RD[7:0] This port is for designers to read data to RS232 interface. Offset 8Bh ....................................................................................... Default value = 8'h00
ROMADDR7 ROMADDR6 ROMADDR5 ROMADDR4 ROMADDR3 ROMADDR2 ROMADDR1 ROMADDR0
-
-
-
-
-
-
-
-
7-0 ROMADDR[7:0] Offset 8Ch
This port is for designers to write address and commands to 93C46.
ROMWD15 ROMWD14 ROMWD13 ROMWD12 ROMWD11 ROMWD10 ROMWD9 ROMWD8 7-0 ROMWD[15:8] This port is for designers to write data to 93C46. Offset 8Dh ROMWD7 ROMWD6 ROMWD5 ROMWD4 ROMWD3 ROMWD2 ROMWD1 ROMWD0 7-0 ROMWD[7:0] Offset 8Eh ROMRD15 ROMRD14 ROMRD13 ROMRD12 ROMRD11 ROMRD10 ROMRD9 7-0 ROMRD[15:8] This port is for designers to read data to 93C46. Offset 8Fh ROMRD7 ROMRD6 ROMRD5 ROMRD4 ROMRD3 ROMRD2 ROMRD1 ROMRD0 ROMRD8 This port is for designers to write data to 93C46.
7-0 ROMRD[7:0]
This port is for designers to read data to 93C46.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 57
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 90h ....................................................................................... Default value = 8'h00 X X X X X X X X RREFED11 RREFED10 RREFED9 RREFED8 R/W R/W R/W R/W
7-4 RESERVED 4-0 RREFED[11:8] Pre-feed steps for ADF (or sheetfed scanner). Offset 91h ....................................................................................... Default value = 8'h00 RREFED7 RREFED6 RREFED5 RREFED4 RREFED3 RREFED2 RREFED1 RREFED0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 RREFED[7:0] Pre-feed steps for ADF (or sheetfed scanner).
Scanning Window
Document Sheet
Document
ADF Sensor PREFED
Sensor
Note:
If the DPI9600 control bit is set to "1", the STRPIXEL is doubled.
Offset 92h ....................................................................................... Default value = 8'h00 PSTFED15 PSTFED14 PSTFED13 PSTFED12 PSTFED11 PSTFED10 PSTFED9 R/W R/W R/W R/W R/W R/W R/W PSTFED8 R/W
7-0 PSTFED[15:8] Past scanning steps for ADF (or sheetfed scanner). Offset 93h ....................................................................................... Default value = 8'h00 PSTFED7 R/W PSTFED6 R/W PSTFED5 R/W PSTFED4 R/W PSTFED3 R/W PSTFED2 R/W PSTFED1 R/W PSTFED0 R/W
7-0 PSTFED[7:0]
Past scanning steps for ADF (or sheetfed scanner).
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 58
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Scanning Window
Document Sheet
Document
ADF Sensor
Sensor
PSTFED
Offset 94h ....................................................................................... Default value = 8'h00 MTRPLS7 MTRPLS6 MTRPLS5 MTRPLS4 MTRPLS3 MTRPLS2 MTRPLS1 MTRPLS0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 MTRPLS[7:0] Pulse width of ADF motor trigger signal (GPIO6). It's valid when ADFSEL = 1.
Offset 95h ....................................................................................... Default value = 8'h00 X X X X X X X X
SCANLEN19 SCANLEN18 SCANLEN17 SCANLEN16
R/W
R/W
R/W
R/W
7-4 RESERVED 4-0 SCANLEN[19:16] Scanning length limitation of ADF (or sheetfed scanner). If the scanned lines are lager than this value but document sensor is still active (DOC_SENR is high), the paper-jam bit (bit 3 in Reg 40) will be set. Offset 96h ....................................................................................... Default value = 8'h00
SCANLEN15 SCANLEN14 SCANLEN13 SCANLEN12 SCANLEN11 SCANLEN10 SCANLEN9 SCANLEN8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 SCANLEN[8:15] Scanning length limitation of ADF (or sheetfed scanner). If the scanned lines are lager than this value but document sensor is still active (DOC_SENR is high), the paper-jam bit (bit 3 in Reg 40) will be set. Offset 97h ....................................................................................... Default value = 8'h00
SCANLEN7 SCANLEN6 SCANLEN5 SCANLEN4 SCANLEN3 SCANLEN2 SCANLEN1 SCANLEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 SCANLEN[7:0] Scanning length limitation of ADF (or sheetfed scanner). If the scanned lines are lager than this value but document sensor is still active (DOC_SENR is high), the paper-jam bit (bit 3 in Reg 40) will be set. Offset 98h ....................................................................................... Default value = 8'h00 ONDUR15 ONDUR14 ONDUR13 ONDUR12 ONDUR11 ONDUR10 R/W R/W R/W R/W R/W R/W 7-0 ONDUR[15:8] On duration (in system clock) of PWM for LAMP control. ONDUR9 R/W ONDUR8 R/W
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 59
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 99h ....................................................................................... Default value = 8'h00 ONDUR7 R/W ONDUR6 R/W ONDUR5 R/W ONDUR4 R/W ONDUR3 R/W ONDUR2 R/W ONDUR1 R/W ONDUR0 R/W
7-0 ONDUR[7:0]
On duration (in system clock) of PWM for LAMP control.
Offset 9Ah ....................................................................................... Default value = 8'h00 OFFDUR15 OFFDUR14 OFFDUR13 OFFDUR12 OFFDUR11 OFFDUR10 OFFDUR9 OFFDUR8 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 OFFDUR[15:8] Off duration (in system clock) of PWM for LAMP control. Offset 9Bh ....................................................................................... Default value = 8'h00 OFFDUR7 OFFDUR6 OFFDUR5 OFFDUR4 OFFDUR3 OFFDUR2 OFFDUR1 OFFDUR0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 OFFDUR[7:0] Offset 9Ch LCMWD7 LCMWD6 LCMWD5 LCMWD4 LCMWD3 LCMWD2 LCMWD1 LCMWD0 Off duration (in system clock) of PWM for LAMP control.
7-0 LCMWD[7:0]
This port is for designers to write data to LCM.
Offset 9Dh ....................................................................................... Default value = 8'h00 RAMDLY1 RAMDLY0 MOTLAG R/W R/W R/W CMODE R/W STEPTIM1 STEPTIM0 R/W R/W
MULDMYLN
R/W
IFRS R/W
7-6 RAMDLY[1:0] Select timing delay for SCLK of SDRAM. 5 MOTLAG 0 Do not force the trigger position of motor trigger. 1 Force motor to locate its trigger at the end of line when dummy lines function is activated. 4 CMODE 0 Select two-pin type control for COM1 & COM2 of LCD (GPO29&30). 1 Select three-pin type control for COM1 & COM2 of LCD (GPIO10, GPO29&30). 3-2 STEPTIM[1:0] Select the multiplier of slope table. For Reg 21, 24, 5F, 69, 6A, the real slope steps are register values multiplied by STEPTIM. STEPTIM[1:0] =00 : Slope steps = register values =01 : Slope steps = register values * 2 =10 : Slope steps = register values * 4 =11 : Reserved 1 MULDMYLN 0 Set dummy lines are equal to LINESEL. 1 Set dummy lines are equal to LINESEL*2 0 IFRS 0 Select data writing for LCM. 1 Select address writing for LCM.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 60
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset 9Eh ....................................................................................... Default value = 8'h00 X X 7 6 5-3 2-0 SEL3INV TGSTIME2 TGSTIME1 TGSTIME0 TGWTIME2 TGWTIME1 TGWTIME0 R/W R/W R/W R/W R/W R/W R/W
RESERVED SEL3INV TGSTIME[2:0]
To invert SEL3 signals for NEC8884. To set the times of TGSHLD[4:0] . So , the width is TGSHLD[4:0]* 2 TGSTIME TGWTIME[2:0] To set the times of TGW[5:0] . So, the width is TGW[5:0]* 2 TGWTIME
Offset 9Fh ....................................................................................... Default value = 8'h00
LCDCTL LCMCTL EPROMCTL TGCTL MPUCTL
MOTMPU R/W
NEC8884 R/W
DPI960 R/W
R/W
R/W
R/W
R/W
R/W
7 LCDCTL 6 LCMCTL 5 EPROMCTL 4 TGCTL 3 MPUCTL 2 MOTMPU
1 0
To control LCD timing when LCD function is enabled. To control LCD timing when LCM function is enabled. To control LCD timing when EEPROM function is enabled. To enable special CCD TG modes. To enable work styles when designer use internal RISC CPU. To select motor trigger output to MPU. The MPU can process the trigger signal. Note: If designer set MOTMPU=1 then he must set ACDCDIS=1. NEC8884 To enable NEC8884 SEL3 function. DPI9600 To enable 9600d resolution.
Offset A0h ....................................................................................... Default value = 8'h00 X X X X LNOFSET5 LNOFSET4 LNOFSET3 LNOFSET2 LNOFSET1 LNOFSET0 R/W R/W R/W R/W R/W R/W
7-6 RESERVED 5-0 LNOFSET[5:0] Line difference of R, G, B in packing three channels to one color line. Offset A1h ....................................................................................... Default value = 8'h00 X X X X X X STGSET4 R/W STGSET3 R/W STGSET2 R/W STGSET1 R/W STGSET0 R/W
7-5 RESERVED 4-0 STGSET[4:0]
Line difference of stagger CCD between even and odd lines in packing them to the same color line.
Offset A2h ....................................................................................... Default value = 8'h00 X X X X X X RFHSET4 R/W RFHSET3 R/W RFHSET2 R/W RFHSET1 R/W RFHSET0 R/W
7-5 RESERVED 4-0 RFHSET[4:0]
Refresh time of SDRAM. The unit is 2us. Page 61
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset A3h ....................................................................................... Default value = 8'h00 TRUER7 R/W TRUER6 R/W TRUER5 R/W TRUER4 R/W TRUER3 R/W TRUER2 R/W TRUER1 R/W TRUER0 R/W
7-0 TRUER[7:0]
Weighting of R channel in true gray scanning.
Offset A4h ....................................................................................... Default value = 8'h00 TRUEG7 R/W TRUEG6 R/W TRUEG5 R/W TRUEG4 R/W TRUEG3 R/W TRUEG2 R/W TRUEG1 R/W TRUEG0 R/W
7-0 TRUEG[7:0]
Weighting of G channel in true gray scanning.
Offset A5h ....................................................................................... Default value = 8'h00 TRUEB7 R/W TRUEB6 R/W TRUEB5 R/W TRUEB4 R/W TRUEB3 R/W TRUEB2 R/W TRUEB1 R/W TRUEB0 R/W
7-0 TRUEB[7:0]
Weighting of B channel in true gray scanning.
Offset A6h ....................................................................................... Default value = 8'h00 GPIO24 R/W GPIO23 R/W GPIO22 R/W GPIO21 R/W GPIO20 R/W GPIO19 R/W GPIO18 R/W GPIO17 R/W
7-0 GPIO[24:17]
GPIO24~17 input/output ports.
Offset A7h ....................................................................................... Default value = 8'h00 GPOE24 R/W GPOE23 R/W GPOE22 R/W GPOE21 R/W GPOE20 R/W GPOE19 R/W GPOE18 R/W GPOE17 R/W
7-0 GPOE[24:17]
Select directions of GPIO24~17 ports. They can be set to different values independently. 0 Set as input port. 1 Set as output port.
Offset A8h ....................................................................................... Default value = 8'h00 X X X X GPOE27 R/W GPOE26 R/W GPOE25 R/W GPIO27 R/W GPIO26 R/W GPIO25 R/W
7-6 RESERVED 5-3 GPOE[27:25]
2-0 GPIO[27:25]
Select directions of GPIO27~25 ports. They can be set to different values independently. 0 Set as input port. 1 Set as output port. GPIO27~25 input/output ports.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 62
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset A9h ....................................................................................... Default value = 8'h00 X X 7-6 RESERVED 5-0 GPO[33:28] X X GPO33 R/W GPO32 R/W GPO31 R/W GPO30 R/W GPO29 R/W GPO28 R/W
GPO33~28 output ports.
Offset ABh ....................................................................................... Default value = 8'h00 GPOM9 R/W
MULSTOP2 MULSTOP1 MULSTOP0 NODECEL TB3TB1 TB5TB2
R/W
R/W
R/W
R/W
R/W
R/W
FIX16CLK R/W
7-6 GPOM9
0 Select GPIO9 as general purpose I/O. 1 Select GPIO9 as V-ref control of bipolar motor driver IC to control Imax
6-4 MULSTOP[2:0] Select stop time of motor start/stop. The stop time = STOPTIM * 2 MULSTOP 3 NODECEL 0 Motor decelate when carriage touch home sensor 1 Motor doesn't decelerate when carriage touch home sensor 2 TB3TB1 0 Don't replace. 1 Use table 1 of motor table to replace table 3. 1 TB5TB2 0 Don't replace. 1 Use table 2 of motor table to replace table 5. 0 FIX16CLK To enable 16 system clocks/pixel recover function Offset ACh ....................................................................................... Default value = 8'h00 VRHOME3 VRHOME2 VRMOVE3 VRMOVE2 VRBACK3 R/W R/W R/W R/W R/W 7-6 VRHOME[3:2] 5-4 VRMOVE[3:2] 3-2 VRBACK[3:2]
VRBACK2 VRSCAN3 VRSCAN2
R/W
R/W
R/W
Vref of the motor driver IC for go-home moving Vref of the motor driver IC for fast forward moving Vref of the motor driver IC for backward moving when the image buffer is full
Offset ADh ....................................................................................... Default value = 8'h00 X X X X Set ADF types like one pass, U-turn, forward & backward. Set 600 * 2 , 1200 * 2 , 2400 * 2 , 1200 * 4 , 1200 * 2 + 600 , 1200 * 4 + 600 CCD types. ADFTYP1 ADFTYP0 R/W R/W
CCDTYP3 CCDTYP2 CCDTYP1 CCDTYP0
R/W
R/W
R/W
R/W
7-6 RESERVED 5-4 ADFTYP[5:4] 3-0 CCDTYP[3:0]
Offset AEh ....................................................................................... Default value = 8'h00 X X 7-6 RESERVED X X Set the working methods of motor motor driver IC under ADF feeding. Set data flow process under scanning. Page 63 MOTSET2 MOTSET1 MOTSET0 PROCESS2 PROCESS1 PROCESS0 R/W R/W R/W R/W R/W R/W
5-3 MOTSET[5:3] 2-0 PROCESS[2:0]
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Offset AFh ....................................................................................... Default value = 8'h00
SCANTYP2 SCANTYP1 SCANTYP0 FEDTYP1 FEDTYP0
ADFMOVE2 ADFMOVE1 ADFMOVE0
R/W 7-5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCANTYP[2:0]
Set scanning types under ADF working. Set feeding types for ADF fast moving.
4-3 FEDTYP [4:3]
2-0 ADFMOVE [2:0] Set document-in moving types for ADF.
4.3 Register Mapping 4.3.1 Shading Mapping (Chunky for Single Bank)
Table 4.2 - Shading Mapping (Chunky for Single Bank)
Attribute Resolution 600dpi (DPIHW=00) 1200dpi (DPIHW=01) 2400dpi (DPIHW=10) 4800dpi (DPIHW=11) Address[24:0] 0000000H~00083FFH SIZE : 33k 0000000H~00107FFH SIZE : 66k 0000000H~0020FFFH SIZE : 132k 0000000H~0041FFFH SIZE : 264k
Shading Mapping
4.3.2 Shading Mapping (Chunky for Double Bank)
Table 4.3 - Shading Mapping (Chunky for Double Bank)
Attribute Resolution 600dpi (DPIHW=00) BABK0 BANK1 BANK0 BANK1 BANK0 BANK1 BANK0 BANK1 Address[24:0] 0000000H~00041FFH SIZE : 16.5K 0004200H~00083FFH SIZE : 16.5K 0000000H~00083FFH SIZE : 33K 0008400H~00107FFH SIZE : 33K 0000000H~00107FFH SIZE : 66K 0010800H~0020FFFH SIZE : 66K 0000000H~0020FFFH SIZE : 132K 0021000H~0041FFFH SIZE : 132K
1200dpi (DPIHW=01) Shading Mapping 2400dpi (DPIHW=10)
4800dpi (DPIHW=11)
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 64
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 4.3.3 Image Buffer Mapping
Table 4.4 - Image Buffer Mapping
Attribute Resolution R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd Address[24:0] 0008400H~00317FFH(165k) 0031800H~005ABFFH(165k) 005AC00H~0083FFFH(165k) 0084000H~00AD3FFH(165k) 00AD400H~00D67FFH(165k) 00D6800H~00FFBFFH(165k) 00FFC00H~00FFFFFH(1k) 0010800H~00383FFH(159k) 0038400H~005FFFFH(159k) 0060000H~0087BFFH(159k) 0087C00H~00AF7FFH(159k) 00AF800H~00D73FFH(159k) 00D7400H~00FEFFFH(159k) 00FF000H~00FFFFFH(4k) 0021000H~0045FFFH(148k) 0046000H~006AFFFH(148k) 006B000H~008FFFFH(148k) 0090000H~00B4FFFH(148k) 00B5000H~00D9FFFH(148k) 00DA000H~00FEFFFH(148k) 00FF000H~00FFFFFH(4k) 0042000H~00617FFH(126k) 0061800H~0080FFFH(126k) 0081000H~00A07FFH(126k) 00A0800H~00BFFFFH(126k) 00C0000H~00DF7FFH(126k) 00DF800H~00FEFFFH(126k) 00FF000H~00FFFFFH(4k) 0008400H~00B17FFH(677k) 00B1800H~015ABFFH(677k) 015AC00H~0203FFFH(677k) 0204000H~02AD3FFH(677k) 02AD400H~03567FFH(677k) 0356800H~03FFBFFH(677k) 03FFC00H~03FFFFFH(1k) 0010800H~0B83FFH(671k) 00B8400H~15FFFFH(671k) 0160000H~207BFFH(671k) 0207C00H~2AF7FFH(671k) 02AF800H~3573FFH(671k) 0357400H~3FEFFFH(671k) 03FF000H~3FFFFFH(4k) 0021000H~00C5FFFH(660k) 00C6000H~016AFFFH(660k) 016B000H~020FFFFH(660k) 0210000H~02B4FFFH(660k) 02B5000H~0359FFFH(660k) 035A000H~03FEFFFH(660k) 03FF000H~03FFFFFH(4k) 0042000H~00E17FFH(638k) Page 65
600DPI (DPIHW=00)
1200DPI (DPIHW=01) SDRAM 16M BITS X 1 [19:0] 2400DPI (DPIHW=10)
4800DPI (DPIHW=11)
SDRAM 64M BITS X 1 [21:0]
600DPI (DPIHW=00)
1200DPI (DPIHW=01)
2400DPI (DPIHW=10)
4800DPI (c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
(DPIHW=11) R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy 00E1800H~0180FFFH(638k) 0181000H~02207FFH(638k) 0220800H~02BFFFFH(638k) 02C0000H~035F7FFH(638k) 035F800H~03FEFFFH(638k) 03FF000H~03FFFFFH(4k) 0010800H~0162FFFH(1354k) 0163000H~02B57FFH(1354k) 02B5800H~0407FFFH(1354k) 0408000H~055A7FFH(1354k) 055A800H~06ACFFFH(1354k) 06AD000H~07FF7FFH(1354k) 07FF800H~07FFFFFH(2k) 0021000H~0170BFFH(1343k) 0170C00H~02C07FFH(1343k) 02C0800H~04103FFH(1343k) 0410400H~055FFFFH(1343k) 0560000H~06AFBFFH(1343k) 06AFC00H~07FF7FFH(1343k) 07FF800H~07FFFFFH(2k) 0042000H~018C3FFH(1321k) 018C400H~02D67FFH(1321k) 02D6800H~0420BFFH(1321k) 0420C00H~056AFFFH(1321k) 056B000H~06B53FFH(1321k) 06B5400H~07FF7FFH(1321k) 07FF800H~07FFFFFH(2k) 0010800H~0162FFFH(1354k) 0163000H~02B57FFH(1354k) 02B5800H~0407FFFH(1354k) 0408000H~055A7FFH(1354k) 055A800H~06ACFFFH(1354k) 06AD000H~07FF7FFH(1354k) 07FF800H~07FFFFFH(2k) 0008400H~02B17FFH(2725k) 02B1800H~055ABFFH(2725k) 055AC00H~0803FFFH(2725k) 0804000H~0AAD3FFH(2725k) 0AAD400H~0D567FFH(2725k) 0D56800H~0FFFBFFH(2725k) 0FFFC00H~0FFFFFFH(1k) 0010800H~02B83FFH(2719k) 02B8400H~055FFFFH(2719k) 0560000H~0807BFFH(2719k) 0807C00H~0AAF7FFH(2719k) 0AAF800H~0D573FFH(2719k) 0D57400H~0FFEFFFH(2719k) 0FFFF000H~0FFFFFFH(4k) 0021000H~02C5FFFH(2708k) 02C6000H~056AFFFH(2708k) 056B000H~080FFFFH(2708k) 0810000H~0AB4FFFH(2708k) 0AB5000H~0D59FFFH(2708k) 0D5A000H~0FFEFFFH(2708k) 0FFFF000H~0FFFFFFH(4k) Page 66
600DPI (DPIHW=00)
1200DPI (DPIHW=01) SDRAM 128M BITS X 1 [22:0] 2400DPI (DPIHW=10)
4800DPI (DPIHW=11)
SDRAM 256M BITS X 1 [23:0]
600DPI (DPIHW=00)
1200DPI (DPIHW=01)
2400DPI (DPIHW=10)
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy R_odd R_even G_odd G_even B_odd B_even Dummy 0042000H~02E17FFH(2686k) 02E1800H~0580FFFH(2686k) 0581000H~08207FFH(2686k) 0820800H~0ABFFFFH(2686k) 0AC0000H~0D5F7FFH(2686k) 0D5F800H~0FFEFFFH(2686k) 0FFFF000H~0FFFFFFH(4k) 0008400H~055BFFFH(5455k) 055C000H~0AAFBFFH(5455k) 0AAFC00H~10037FFH(5455k) 1003800H~15573FFH(5455k) 1557400H~1AAAFFFH(5455k) 1AAB000H~1FFEBFFH(5455k) 1FFEC00H~1FFFFFFH(5k) 0010800H~0562FFFH(5450k) 0563000H~0AB57FFH(5450k) 0AB5800H~1007FFFH(5450k) 1008000H~155A7FFH(5450k) 155A800H~1AACFFFH(5450k) 1AAD000H~1FFF7FFH(5450k) 1FFF800H~1FFFFFFH(2k) 0021000H~0570BFFH(5439k) 0570C00H~0AC07FFH(5439k) 0AC0800H~10103FFH(5439k) 1010400H~155FFFFH(5439k) 1560000H~1AAFBFFH(5439k) 1AAFC00H~1FFF7FFH(5439k) 1FFF800H~1FFFFFFH(2k) 0042000H~058C3FFH(5417k) 58C400H~0AD67FFH(5417k) AD6800H~1020BFFH(5417k) 1020C00H~156AFFFH(5417k) 156B000H~1AB53FFH(5417k) 1AB5400H~1FFF7FFH(5417k) 1FFF800H~1FFFFFFH(2k)
4800DPI (DPIHW=11)
600DPI (DPIHW=00)
1200DPI (DPIHW=01) SDRAM 512M BITS X 1 [24:0] 2400DPI (DPIHW=10)
4800DPI (DPIHW=11)
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 67
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 5
BLOCK DIAGRAM
5.1 USB2.0 System Block Diagram
IO Device Motor Driver CCD/CIS
Host
GL843 (USB2.0 Interface+Scanner ASIC Controller) Two-In-One Controller
12 MHz
SDRAM
AFE
Figure 5.1 - USB2.0 System Block Diagram
5.2 Function Block Diagram
Host
USB2.0 Controller
EPP Circuit
Data Interface Control Register
Read/Writ
Data Packing
Black & White
CCD/CIS
Control
CCD/CIS
Data
Compression
A/D Data
Front End
Latch
(16 Bits)
Motor Driver ADF Device
Motor Control ADF Control
Scanner Flow Control
Line Packing Gamma
Correction
True Gray DPI Control White Shading Average Control Dark Shading
12 MHz
PLL
Clk-gen
Motor Moving Table
GPIO Control
I/O Device
Shading, Image SDRAM
Figure 5.2 - Function Block Diagram
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 68
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 6
1 System Clock
FUNCTIONAL DESCRIPTION
Internal PLL. A. Input: 12MHz crystal. B. Output: 12, 24, 30, 40, 48 or 60 MHz to scanner controller system.
2 Pixel Clock
A. Normal mode Scan mode 0: a. 12 system clock/pixel. b. Chunky color (three line in), gray or art scanning for CCD. c. Planar color scan (one line in) or Monochrome scanning for CIS.
B. Scan mode 7 a. 16 system clock/pixel. b. Chunky color (three line in), gray or line-art scanning for CCD. c. Planar color scan (one line in) or Monochrome scanning for CIS. C. Scan mode 6 a. 18 system clock/pixel b. Chunky color (three line in), gray or art scanning for CCD. c. Planar color scan (one line in) or Monochrome scan for CIS. Note: Chunky Color is R1G1B1, R2G2B2, R3G3B3,.........(three-line-in or pixel rate). Planar Color is R1, R2, R3,.....; G1, G2, G3,.......; B1, B2, B3,........(one-line-in or line rate). CCD: Chunky color or planar color. CIS: Planar color.
3 Scan Speed
A. System clock = 30MHz: a. Normal Mode: Chunky color, fine gray or fine line art scan. (scan mode 0) 12x33.333ns/pixel = 0.4us/pixel. (1). 600dpi: 2.160ms/line, 15.163s/page. (2). 1200dpi: 4.320ms/line, 60.653s/page. B. System clock = 40MHz: a. Normal Mode: Chunky color, fine gray or fine line art scan. 12x25ns/pixel = 0.3us/pixel (1). 600dpi: 1.620ms/line, 11.372s/page. (2). 1200dpi: 3.240ms/line, 45.488s/page.
4 Fast Scan for Low Resolutions
Designers are allowed to increase CCD clock rates to up scanning speed in low resolutions, such as 2, 4, 8, ...times..
5 Scanning Type
GL843 supports three-line-in (parallel) for CCD and one-line-in for CIS. A. CCD Type CCD Exposure control There are three modes to control CCD TG by TGMODE control bits. Mode 0: single exposure time for R, G and B channels. Mode 1, 2: different exposure times for R, G and B channels .
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 69
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Timing diagrams: a.TGMODE=00 T6 is the exposure time for each color.
b. TGMODE=01 T3.T4 and T5 is the shift time of image data. T_R is the exposure time of R channel. T_G is the exposure time of G channel. T_B is the exposure time of B channel..
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 70
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
c. TGMODE=10 T1 is the shift time of image data. T2 is for dummy lines. T_R is the exposure time of R channel. T_G is the exposure time of G channel. T_B is the exposure time of B channel..
d. TGMODE=00 T_R , T_G and T_B are the exposure times for three channels.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 71
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
B. CIS Type a. Color scan:
TG
LED R
LED G
LED B
b. Gray scan:
TG
LED R/G/B
c. True gray scan:
TG
LED R
LED G
LED B
6 Image Sensor Timing
Image sensor timings can be programmed by S/W. A. For CCD: Support 600, 1200, 2400, 3200, 3600 ,4800dpi ~ 9600dpi CCD such as NEC, TOSHIBA, Sony ......etc. B. For CIS: Support 600, 1200, 2400, 3200, 3600,4800dpi ~ 9600dp CIS such as TOSHIBA, Canon ......etc.
7 Dummy Line
GL843 supports programmable dummy lines to resolve (overcome) start/stop problem. Designers can insert dummy lines to reduce scanner start/stop events (buffer full). A. Line base of dummy lines: The range of dummy lines is 0~30 lines. B. Adjustable dummy line: T h e r an g e i s fr om t h e m i n i m um sh i ft t i m e of C C D/ CI S up t o 20 96 K pi x el t i m e , with 1 pixel time resolution.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 72
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 8 Support Analog Front End Timing
GL843 supports external 16 bits front-end. Wolfson: WM8192, WM8199, ...etc. Analog device: AD9826, ...etc.
9 Image Type
A. Supports color, gray and line art scanning. B. Supports color filters options (R, G or B channels) in gray or line art scanning. C. Supports true gray with programmable R, G and B weightings.
10 Bits Depth
16*3 bits color, 16 bits gray level and 1 bit line art (Black & White). Image data type: 16 bits, 8 bits and 1 bit.
11 Shading & Correction
a. White Shading & Dark Shading: White shading and dark shading are pixel-by-pixel corrections with 16-bit solution and can be enabled or disabled by S/W. The white shading curve is calculated by S/W. Data arrangement: three line in mode: dark R1, white R1, dark G1, white G1, dark B1, white B1, dark R2, white R2, dark G2, white G2, dark B2, white B2, dark R3, white R3, dark G3, white G3, dark B3, white B3, one line in mode: dark R1, white R1, dark R2, white R2, dark R3, white R3... dark G1, white G1, dark G2, white G2, dark G3, white G3... dark B1, white B1, dark B2, white B2, dark B3, white B3... White shading formula: 2000H * Target / (Wn-Dn) = White Gain data ----- for 8 times system White shading formula: 4000H * Target / (Wn-Dn) = White Gain data ----- for 4 times system For example: Target = 3FFFH, Wn = 2FFFH, Dn = 0040H and 8 times system operation then White Gain = 2000H * 3FFFH / (2FFFH-0040H) = 2AE4H (1.34033 times) b. Gamma Correction: 16-bit GAMMA correction table is programmed by S/W. Range: 0 ~ 64k (16 bits) input mapping to 0 ~ 255 (8 bits) output. Style: increment or decrement gamma curve Note: 16 bits image data will be mapped to 8 bits data by gamma table. Designer can get 16 bit image data by disabling gamma table.
12 Threshold Setting for Line-Art
Threshold can be programmed by S/W. Range: 0 ~ 255 adjustable. The threshold with hysteresis characteristic is for reducing image noise. BWHI BWLOW b c d e f h i hysteresis width
g a a,b,c,g : are black pixels d,e,f,h,i : are white pixels
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 73
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 13 Exposure Time
Maximum: 2096k pixels time Adjustment step: 1 pixel time. For transparency scanning, the exposure time can be up to 2096k pixels time.
14 Scan Width control for Horizontal Line
a. Supports start and end pixels assignment in setting scan width. b. Scanning width= end pixels - start pixels Maximum length: 128K pixels. Minimum length: 1 pixel.
15 Support built-in USB 2.0 Controller
2-in-1 USB2.0 controller + scanner controller.
16 SDRAM Timing
Supports 16M Bits (1M*16), 64M Bits (4M*16), 128M Bits (8M*16), 256M Bits (16M*16) and 512 M Bits (32M*16) SDRAM as image buffer and calibration buffer.
17 Horizontal Resolution Adjustable for DPI Function
A. Digital deletion type: Software adjustable resolutions range from 9600 to 1 dpi with 1 dpi decrement. B. Digital average type: Supports 1/2, 1/3, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/15 digital average function. For example, options for 1200dpi scanner are: 1200dpi, 600dpi, 400dpi, 300dpi, 240dpi, 200dpi, 150dpi,120dpi, 100dpi, 80dpi by average function. C. Support stagger CCD: Supports 1/2, 1/4, 1/8 resolutions, such as NEC Toshiba and Sony stagger CCD.
18 Vertical Resolution Adjustable for DPI Function
The resolution of motor moving is 16 bits wide and is flexibly controlled by motor tables. The resolution can be up to 4800 dpi for 1200 dpi scanners, 9600 dpi for 2400 dpi scanners and 19200 dpi for 4800 dpi scanners. Note: The resolution of vertical direction of quarter step can up to four times resolution.
19 Five Acceleration/Deceleration Tables
The acceleration/deceleration tables are stored in internal SRAM and can be downloaded by S/W. And the resolution is 16 bits in pixel-time. The number of table steps is from 1 to 1020 steps for arbitrary curves. There are five tables for motor moving. Three tables are for scanning and the others are for fast moving. The forward and backward steps can be programmed by S/W separately. Note: "Fast move" means move back to home position or move forward to scan window in any position.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 74
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
(1) Two tables type: Speed Scanning position Buffer full position Scan finished
Go to scan window forward A(4) B(4) C(1) D(1) E(1) F(3) Length G(5),K go home A,J B C,D E F I H G K H(2) I(2) backward J(4)
: Acceleration curve in table four (slope four) for fast moving. : Deceleration curve in table four (slope four) for fast moving. : Acceleration curve in table one (slope one) for scanning. : Deceleration curve in table one (slope one) for scanning. : Deceleration curve in table three (slope three) for scanning finished to protect wall hitting. : Acceleration curve in table two (slope two) for back-track when image buffer full. : Deceleration curve in table two (slope two) for back-track when image buffer full. : Deceleration curve in table five (slope five) for go-home to protect wall hitting. : Touch home sensor deceleration curve for go-home.
(2) One tables type: Speed Scanning position Buffer full position Scan finished
Go to scan window C(1) D(1) E(1) F(3) Length G(5),K Go home J C,D E F I H G K : Acceleration curve in table four (slope four) for fast moving. : Acceleration curve in table one (slope one) for forward scanning. : Deceleration curve in table one (slope one) for scanning. : Deceleration curve in table three (slope three) for scanning finished to protect wall hitting. : Acceleration curve in table two (slope two) for back-track when image buffer full. : Deceleration curve in table two (slope two) for back-track when image buffer full. : Deceleration curve in table five (slope five) for go-home to protect wall hitting. : Touch home sensor deceleration curve for go-home. H(2) I(2) J(4)
20 Trigger Position Control
Designers can select to move motor first then capture image; or capture image first then move motor.
21 Stepping Motor Phase Control
There are 8 output control pins to control stepping motors: (c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 75
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
MTR_PH 0~7 for bipolar motors MTR_PH 0~3 for unipolar motors A. Bipolar motors: a. Supports 2916 motor driver timing and 2916 compatible driver IC, such as L6219. Include full, half and quarter steps control. b. Supports 3955 motor driver timing. Include full, half, quarter and eighth steps control. c. Supports 3967 motor driver timing. Include full, half, quarter and eighth steps control. d. Supports LB1939, 1940 motor driver timing. Include full and half steps control B. Unipolar motors: a. Supports 2003 motor driver timing and 2003 compatible driver IC. b. Include full step two phases on, full step single phase on and half step. c. PWM control, include frequency and duty controls.
PWM Duty Frequency
Phase on time
22 Watchdog Protection
This function can automatically reset the system to initial state when the system is hanged (no access signal) beyond the time limit. It can be enabled or disabled by S/W. This function can protect motor power, lamp power and ASIC system. Calculation formula: (30sec.) * (times setting) * (setting number.). The range of setting number is from 1 to 15; the range of times setting is 0 or 1.
23 Lamp Time-out Control
This circuitry can automatically turn off the lamp power when this function is enabled. It can be enabled or disabled by S/W. Calculation formula: (60sec.) * (times setting) * (setting number). The range of setting number is from 1 to 7;the range of times setting is 0 to 3.
24 Lamp Power Control
These are two power control ports for lamp. One is for Flatbed and the other is for XPA (Transparency or film).
These control ports have PWM function. According to the system clock, designers can flexibly adjust their frequency and duty by S/W. And the resolution of PWM is 16 bits.
25 Sensors
The system supports home sensor for flatbed; ADF sensor, document sensor and cover sensor for ADF module.
26 GPIO Ports
Designers can separately assign input or output direction for each GPIO pin of GPIO1~20 and GPIO27. Some GPIO can be designed for keypads, document sensor of sheetfed or motor power control...etc. Designers can assign GPIO27 as general-purpose input/output port or as ADF sensor input. Note : There are two pins for special function. One is GPIO12 and the other is GPIO11. GPIO12: 1. Pull up by resistor to indicate ASIC to turn on lamp power in power-on initial state. 2. Pull down by resistor to indicate ASIC to turn off lamp power in power-on initial state.. (c)2000-2006 Genesys Logic Inc. - All rights reserved. Page 76
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
3. This pin can control bipolar motor driver IC (2916,6219,3955 or 3967) Vref for controlling Imax current. GPIO11: This pin can control bipolar motor driver IC (2916,6219,3955 or 3967) Vref for control Imax current.
27 GPO28~33 Ports
GL843 provides 6 ports for general-purpose output. They exist in both 128 and 208 pins packages.
28 Power on Check
The default status of the PWRBIT control bit is reset. Programmers can set the PWRBIT control bit before controlling the ASIC. GL843 will keep the status until power is turn off. This operation is to check if the power had been turned off or not.
29 Extended GPIO
GPIO21~26 is only available in 208 pins QFP package.
30 LED Blinking
GL843 supports LED -blinking function. It is implemented in GPIO15~16 pins and GPIO21~26.
31 Support Back Scanning
GL843 supports forward or backward scanning.
32 Support LCD Interface
GL843 supports LCD display interface via internal logic circuitry. Programmers need to set the LCDSEL control bit to logic `1'.
33 Support LCM Interface
GL843 supports LCM display interface via internal logic circuitry. Programmers need to set the LCMSEL control bit to logic `1'. GPIO19 controls RS of LCM. GPIO20 controls EN of LCM. GPIO1~4 control the data bus of LCM and share the input of keys matrix. GPIO18 controls the /E of external 74HC244. The 74HC244 is a bus buffer to share keys matrix and LCM data bus. Following is the application of keys matrix & LCM display.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 77
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
34 Supports ADF Function
GL843 supports ADF (Auto-document-feeder) function via internal logic circuitry. Programmers need to set the ADFSEL control bit to logic `1'. GPIO6 controls the motor pulse trigger if the motor moving of ADF module is implemented by trigger pulse, otherwise the motor moving is driven by motor phases. GPO28 controls the moving direction of motor if ADF module is necessary. GPIO16 is the cover sensor input, GPIO27 is the ADF sensor input and HOME is document sensor input under ADF mode. Scanning Window
Document Sheet
Document Sensor
ADF Sensor PREFED
GL843 can feed document sheets automatically to scanning window. After sensing the present of document by document sensor, software should issue feed command to GL843 for paper feeding. After document sheet reaches ADF sensor, scanning process will be started after PREFED motor steps.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 78
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Scanning Window
Document Sheet
Document
Sensor
ADF Sensor
PSTFED
When document sheet keeps moving forward, after sensing the absent of document by ADF sensor, scanning process will be terminated after PSTFED scanning lines.
35 Supports RS232 Interface
GL843 supports RS232 interface via internal logic circuitry. Programmers need to set the RS232SEL control bit to logic `1'. GPIO6 transmits the data of RS232 and GPIO28 receives the data of RS232 under RS232 mode. The baud rate can be programmed to 2400,4800, 9600 and 19200 bps by S/W.
36 Supports EEPROM (93C46) Interface
GL843 supports EEPROM interface via internal logic circuitry. Programmers need to set the EPROMSEL control bit to logic `1'. GPIO1 controls SK of external EEPROM, GPIO2 controls DI/DO of EEPROM and GPIO17 controls CS of external EEPROM under EEPROM mode.
37 Embedded RISC CPU for Scanning, Run-in and Diagnostic Tests
GL843 embeds a powerful RISC CPU. It has timers, counters and interrupt ports. Designers can use the embedded CPU to do the run-in, diagnostic tests and anything he wants to do.
38 Supports External 24Kbytes flash ROM or Internal 24Kbyte mask ROM
Designers can use 24K bytes embedded mask ROM or external flash ROM. Firmware can be downloaded to flash ROM directly by PC S/W. It provides a flexible development environment to design the firmware.
39 Supports Key-Matrix with Latch Function
Designers need to set MATRIXEN control bit to logic `1' to enable key-matrix function. GPIO13~15 are the scanning output of key-matrix and GPIO1~4 are the scanning input of key-matrix. Designers can select 1*4, 2*4 or 3*4 matrix for different applications. By resetting MATRIXEN to logic `0', designers can directly use GPIO1~4 as four hot keys inputs. Any hot key status is latched into key buffer until it is read out.
40 "True gray" with R,G and B weightings
Designers can obtain the "true gray" image data by enabling "true gray" function. Image data is generated by R,G and B outputs and multiplied by weightings. Formula of true gray value = R*(TRUER [7:0]) + G*(TRUEG [7:0]) + B*(TRUEB [7:0])
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 79
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 41 Lossless Data Compression
GL843 use Huffman coding method to implement the lossless data compression.
42 Lines Packing for Stagger CCD or R/G/B Line Differences
GL843 packs R, G and B lines together for CCD sensors by hardware. And it also packs the same color lines of stagger CCD together.
43 Fine CDS Sampling Adjustment
Designers can fine-tune the CDS sampling position to avoid the digital noise influence (8.33ns adjustment). The image noise may come from the digital noise of PCB.
44 Wall-Hitting Protection
Designers can use table five of motor moving to protect the wall hitting. The LONGCURV control bit has to be set to logic `1' to enable the long-curve function. The first several steps are used to decelerate the carriage moving; the other slower steps are focused on touching the home sensor. Due to the special table five, designers can replace the photo-sensor by simple, cheaper mechanical-type sensors.
45 Motor Driver IC Setting
Designers add pull up/pull down resistors on MTR_SEL1~3 will indicate ASIC to generate the timing of specified motor driver IC. Please refer to section 5.2. MTR_SEL1 share in CCD_CH4X pin. MTR_SEL2 share in CCD_TGG pin. MTR_SEL3 share in CCD_TGB pin.
46 Operation Mode Setting
Designers add pull down resistors on TSTSEL1~2 will indicate ASIC to work on normal mode.Please refer to section 5.2. TSTSEL1 share in CCD_CK2X pin. TSTSEL2 share in CCD_RSX.
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 80
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings (Voltage Referenced to GND)
Table 7.1 - Absolute Maximum Ratings (Voltage Referenced to GND)
Symbol DVCC0 DVCC1 AVDD DC supply voltage AVCC1 VccCore1~4 VccIO1~6 DC supply voltage Description Min Max
-0.5V
+3.6V
-0.5V -0.5V -0.5V -0.5V -0.5V -60C 0C
VI DC input voltage VI/O DC input voltage range for I/O VAI/O DC input voltage for USB D+/D- pins VI/OZ DC voltage applied to outputs in High Z state TSTQ Storage temperature range Tamb Operating ambient temperature Note: VCC: VccCore, VccIO, DVCC, AVDD or AVCC1
+3.6V or +5.5V VCC+0.5V VCC+0.5V VCC+0.5V VCC+0.5V +150C 70C
7.2 DC Characteristics (Digital Pins): 3.3 V Logic Core or Pads
Table 7.2 - DC Characteristics (Digital Pins): 3.3 V Logic Core or Pads
SYMBOL Description Min Typ. Max Unit PD Power Dissipation mA DVCC0 DVCC1 AVDD Power Supply Voltage 3.1 3.3 3.6 V AVCC1 VccCore1~4 VccIO1~6 Power Supply Voltage 3.3V 3 3.3 3.6 V DC output sink current excluding IO 16 or 8 mA D+/D-/VCC/GND VIL LOW level input voltage 0.9 V VIH HIGH level input voltage 2.0 V VTLH LOW to HIGH threshold voltage 1.3 1.43 1.56 V VTHL HIGH to LOW threshold voltage 1.3 1.43 1.56 V VHYS Hysteresis voltage 0 V VOL LOW level output voltage when IOL=16mA 0.4 V VOH HIGH level output voltage when IOH=16mA 2.4 V Leakage current for pads with internal pull up IOLK 46 A or pull down resistor RDN Pad internal pulldown resister 72.8K 105.7K 167.4K RUP Pad internal pullup resister 135.9K 167.8K 212.4K Note: hbd16dhk is internal pulled down; hbd16uhk is internal pulled up; hbd16* is 16mA; hbd8* is for 8mA
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 81
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x 7.3 DC Characteristics (Digital Pins): 5.0 V Pads
Table 7.3 - DC Characteristics (Digital Pins): 5.0 V Pads
SYMBOL PD VccIO1~6 IO VIL VIH VTLH VTHL VOL VOH IOLK RDN RUP Description Min Typ. 5.0 Max 5.5 Unit mA V mA 0.9 V V V V V V A
Power Dissipation Power Supply Voltage 5.0V 4.5 DC output sink current excluding 16 D+/D-/VCC/GND LOW level input voltage HIGH level input voltage 2.4 LOW to HIGH threshold voltage HIGH to LOW threshold voltage LOW level output voltage when IOL=8mA HIGH level output voltage when IOH=8mA 2.4 Leakage current for pads with internal pull up or pull down resistor Pad internal pulldown resister 104.6K Pad internal pullup resister 81.9K
0.4 46 159.5K 103.2K 206.6K 254.6K
7.4 DC Characteristics (D+/D-)
Table 7.4 - DC Characteristics (D+/D-)
SYMBOL VOL VOH VDI VCM VSE CIN ILO ZDRV Description
D+/D- static output LOW(RL of 1.5K to 3.6V ) D+/D- static output HIGH (RL of 15K to GND )
Min 2.8 0.2 0.8 0.2 -10 28
Typ.
Max 0.3 3.6 2.5 20 +10 43
Unit V V V V V pF A
Differential input sensitivity Differential common mode range Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 82
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
CHAPTER 8
PACKAGE DIMENSION
MIN(mm) 0.25 2.57 0.10 0.10 13.90 19.90 17.00 23.00 0.65 0
He A2 E A1
Y
QFP-128L (14*20 mm, F/P: 3.2 mm):
SYMBOLS A1 A2 b C D E e Hd He L L1 Y NOM(mm) 0.35 2.72 0.20 0.15 14.00 20.00 0.50 17.20 23.20 0.80 1.60 MAX(mm) 0.45 2.87 0.30 0.20 14.10 20.10 17.40 23.40 0.95 0.08 12
Hd
D
D
b
e
0.08(0.003)
M
H
Figure 8.1 - GL843 128 Pin QFP Package
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 83
L1
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
Figure 8.2- GL843 208 Pin QFP Package
(c)2000-2006 Genesys Logic Inc. - All rights reserved.
Page 84

▲Up To Search▲

Price & Availability of GL843

	To Download GL843 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .